qh25f320s33b8 Numonyx, qh25f320s33b8 Datasheet - Page 24

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qh25f320s33b8

Manufacturer Part Number
qh25f320s33b8
Description
Numonyx? Serial Flash Memory S33
Manufacturer
Numonyx
Datasheet
Figure 12: Supported SPI Bus Operation Modes
8.1.2
Figure 13: Hold State — Standard Usage
Datasheet
24
C - Mode 0
C - Mode 3
HOLD#
S#
C
The Hold State
The HOLD# input signal freezes the internal Clock (C) without resetting the device's
clocking sequence. However, taking HOLD# to V
erase operation that is currently in progress.
To enter the Hold State, the device must be selected (S# at V
on the falling edge of the HOLD# signal, provided that it coincides with the Clock at V
as shown in
provided that it coincides with the SPI Clock at V
If the falling HOLD# edge does not coincide with the Clock at V
after the next falling edge of the Clock as shown in
the rising edge does not coincide with the Clock at V
next falling edge of the Clock.
The command sequence will not necessarily botch if S# is raised to V
at V
HOLD#. If a proper sequence was inputted prior to dropping HOLD# to V
data stream will be recognized as a valid command sequence.
During the Hold State, the Data Output (Q) is at high impedance. The Clock Input and
the Data Input (D) are Don't Care.
S#
Q
D
IL
. Raising S# will complete the command sequence, regardless of the state of
Figure 13 on page
Instruction
Instruction
A23
A22
24. The Hold State ends on the rising edge of HOLD#,
A21
Address
Address
A2
Standard Usage
Hold State
Hold State
A1
IL
IL
.
does not terminate any program or
A0
Figure 14 on page
IL
Numonyx™ Serial Flash Memory (S33)
, the Hold State ends after the
D7
IL
D6
IL
). The Hold State starts
Data
Data
, the Hold State starts
Order Number: 314822-03
D1
IH
25. Similarly, if
while HOLD# is
D0
IL
, the input
December 2007
IL

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