qh25f320s33b8 Numonyx, qh25f320s33b8 Datasheet - Page 23

• Manufacturer Part Number: qh25f320s33b8
• Description: Numonyx? Serial Flash Memory S33
• Manufacturer: Numonyx

Numonyx™ Serial Flash Memory (S33)
8.0
8.1
8.1.1
December 2007
Order Number: 314822-03
Device Operations
This section provides an overview of the Numonyx™ Serial Flash Memory (S33) device
operations.
SPI Bus Operations
The SPI instruction cycle begins with a byte-wide OP Code that is initiated with the
falling edge of S#. The 8-bit instruction is latched into "D" (data input), MSB first, on
the rising edge of "C" (clock).
Some OP Codes are followed by an additional address and dummy and/or data bytes,
MSB first. The number of input instruction bytes depends upon the OP Code. Refer to
Table 15, “SPI Command Set” on page 25
dummy bytes are input through "D" on the rising "C" edge.
Depending upon the OP Code, the data bytes are either input data through "D", or they
are output data from "Q". On cycles that input data through “D”, the output signal “Q”
is at high-Z.
For instructions that change the memory contents or device configuration (such as a
Status Register Write command), the rising S# edge must occur on a whole-byte
increment, otherwise the command will be ignored.
For read operations, the instruction sequence can be botched (ignored) only if S# is
raised before the input sequence is complete. After the required number of input bits is
clocked into the device, a data stream is clocked out of "Q"; each bit is shifted out after
the falling edge of “C” (MSB first). When data is streaming from "Q", raising S# will
terminate the data stream and bring this output to high-Z.
The rising S# edge always resets the SPI command interpreter and places the output in
high-Z. It also does one of the following actions:
When S# is high and the internal algorithms are completed, the device will go into
standby mode.
SPI Modes
This device supports SPI bus operations Mode 0 and Mode 3, as depicted in
“Supported SPI Bus Operation Modes” on page
modes is the default state of the clock signal (C) when the SPI bus master is in
standby. For Mode 0, the “C” is normally low; for Mode 3, “C” is normally high. For both
modes, input data (D) is sampled on the rising edge of “C”, and output data (Q) is
updated on the falling edge of “C.”
• Terminates the output data stream (read operations)
• Kicks off program/erase algorithms
• Initiates changes to the SR
• Botches an SPI command when S# is raised too early (or too late for commands
• Terminates a command and puts the device in standby mode (not in the case of a
that alter the array or device configuration)
program or erase operation)
for the instruction protocols. Address and
24. The difference between the two
Figure 12,
Datasheet
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