gvt7164b18 Cypress Semiconductor Corporation., gvt7164b18 Datasheet

gvt7164b18

Manufacturer Part Number

gvt7164b18

Description

64k X 18 Synchronous Burst Sram Semiconductor

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.GVT7164B18.pdf (13 pages)

Current page: 1 of 13
Download datasheet (190Kb)

297A

Features

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

double-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

Selection Guide

Cypress Semiconductor Corporation

Document #: 38-05204 Rev. *A

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

• Fast access times: 9 and 10 ns

• Fast clock speed: 66 and 50 MHz

• Provide high performance 2-1-1-1 access rate

• Fast OE access times: 5 and 6 ns

• Single +3.3V –5% and +10% power supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst

• Automatic power-down for portable applications

• High-density, high-speed packages

• Low-capacitive bus loading

• High 30-pF output drive capability at rated access time

pipeline

sequence)

SSQ

at all inputs and outputs

•

3901 North First Street

7C1297A-66

7164B18-9

240

9.0

64K X 18 Synchronous Burst SRAM

The CY7C1297A/GVT7164B18 SRAM integrates 65536 × 18

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs

address-pipelining Chip Enable (CE), depth-expansion Chip

Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP,

and ADV), Write Enables (WEL, WEH, and BWE), and Global

Write (GW).

Asynchronous inputs include the Output Enable (OE), Burst

Mode Control (MODE), and Sleep Mode Control (ZZ). The

data outputs (DQ), enabled by OE, are also asynchronous.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

pin (ADV).

Address, data inputs, and Read controls are registered

on-chip to initiate self-timed Write cycle. Write cycles can be

one or two bytes wide as controlled by the Read control inputs.

Individual byte enables allow individual bytes to be written.

WEL controls DQ1–DQ8 and DQP1. WEH controls

DQ9–DQ16 and DQP2. WEL and WEH can be active only with

BWE being LOW. GW being LOW causes all bytes to be

written.

The CY7C1297A/GVT7164B18 operates from a +3.3V power

supply. All inputs and outputs are TTL-compatible. The device

is ideally suited for 486, Pentium®, 680 × 0, and PowerPC™

systems and for systems that benefit from a wide synchronous

data bus.

7C1297A-50

•

7164B18-10

include

10.0

San Jose

240

all

•

addresses,

CA 95134

7C1297A1-50

7164B18-12

Revised January 19, 2003

GVT7164B18

10.0

240

CY7C1297A/

all

•

data

408-943-2600

inputs,

Unit

Related parts for gvt7164b18

gvt7164b18 Summary of contents

Page 1

... Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05204 Rev. *A 64K X 18 Synchronous Burst SRAM The CY7C1297A/GVT7164B18 SRAM integrates 65536 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...

Page 2

... The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. Document #: 38-05204 Rev. *A [1] UPPER BYTE WRITE D Q LOWER BYTE WRITE D Q ENABLE D Q Input Register Address Register CLR Binary Counter and Logic CY7C1297A/ GVT7164B18 DQ1-DQ16 DQP1 DQP2 Page ...

Page 3

... Chip Enable: This active LOW input is used to enable the device and to gate Synchronous ADSP. Input- Chip Enable: This active LOW input is used to enable the device. Synchronous Input- Chip Enable: This active HIGH input is used to enable the device. Synchronous CY7C1297A/ GVT7164B18 A10 CCQ ...

Page 4

... No Connect: These signals are not internally connected. Burst Address Table (MODE = GND First Fourth Address Address (external) (internal) A...A00 A...A11 A...A01 A...A10 A...A10 A...A01 A...A11 A...A00 CY7C1297A/ GVT7164B18 Description Second Third Fourth Address Address Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A10 A...A11 A...A00 A...A11 A...A00 A ...

Page 5

... X H Next CY7C1297A/ GVT7164B18 ADSC ADV WRITE OE CLK ...

Page 6

... Max.; CLK frequency = 0 CC Device deselected; all inputs < > Max CLK cycle time > t min. KC Test Conditions MHz 3.3V CC CY7C1297A/ GVT7164B18 Ambient [9] Temperature V CC 0°C to +70°C 3.3V 5%/+10% Min. Max. 2.0 V +0.3 CCQ –0.3 0.8 –2 2 < V –2 2 OUT CC 2 ...

Page 7

... ALL INPUT PULSES 3.0V 90% 10 1.5 ns (b) (c) Symbol t KQ [23] Description Min [24, 25] 3 [24, 25] [24, 25] 0 [24, 25] [27] 2.5 [27] 0.5 CY7C1297A/ GVT7164B18 Symbol TQFP Typ 200us Vcctyp 90% Vccmin 10% 1.5 ns (d) Typ. Max. 0.016 66 MHz 50 MHz 50 MHz -9 -10 -12 Max. Min. Max. Min ...

Page 8

... This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table. Document #: 38-05204 Rev. *A [23] Description Min. is less than t and t is less than t KQHZ KQLZ OEHZ CY7C1297A/ GVT7164B18 66 MHz 50 MHz 50 MHz -9 -10 -12 Max. Min. Max. Min. . ...

Page 9

... ADV# OE KQLZ DQ SINGLE READ Note: 28. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. Document #: 38-05204 Rev OEQ t OELZ Q(A1) Q(A2) Q(A2+1) CY7C1297A/ GVT7164B18 Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Q(A2+2) Page ...

Page 10

... Timing Diagrams (continued) [28] Write Timing CLK t S ADSP# ADSC ADDRESS A1 WEL#, WEH#, BWE# GW# CE# ADV# OE# t KQX DQ Q SINGLE WRITE Document #: 38-05204 Rev OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE CY7C1297A/ GVT7164B18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE D(A3+2) Page ...

Page 11

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges D(A3) Q(A4) Q(A4+1) Q(A4+2) Single Write Burst Read CY7C1297A/ GVT7164B18 A5 Q(A4+3) D(A5) D(A5+1) Burst Write Page ...

Page 12

... Document #: 38-05204 Rev. *A Package Name Package Type A101 100-lead Thin Quad Flat Pack A101 100-lead Thin Quad Flat Pack A101 100-lead Thin Quad Flat Pack CY7C1297A/ GVT7164B18 Operating Range Commercial Commercial Commercial 51-85050-A Page ...

Page 13

... Document Title: CY7C1297A/GVT7164B18 64K × 18 Synchronous Burst SRAM Document Number: 38-05204 Issue REV. ECN NO. Date ** 112434 02/06/02 *A 123141 01/19/03 Document #: 38-05204 Rev. *A Orig. of Change KOM Change CY part number from CY7C1314A to CY7C1297A RBI Add Power up Requirements to Operating Conditions Information CY7C1297A/ GVT7164B18 Description of Change Page ...

Related keywords

gvt7164b18 datasheet
gvt7164b18 data sheet
gvt7164b18 pdf datasheet
gvt7164b18 component
gvt7164b18 part
gvt7164b18 distributor
gvt7164b18 RoHS
gvt7164b18 datasheet download