gvt7164b18 Cypress Semiconductor Corporation., gvt7164b18 Datasheet - Page 4

• Manufacturer Part Number: gvt7164b18
• Description: 64k X 18 Synchronous Burst Sram Semiconductor
• Manufacturer: Cypress Semiconductor Corporation.

Pin Descriptions
Burst Address Table (MODE = NC/V
Document #: 38-05204 Rev. *A
4, 11, 20, 27, 54, 61,
5, 10, 21, 26, 55, 60,
1–3, 6, 7, 14, 16, 25,
69, 72, 73, 8, 9, 12,
58, 59, 62, 63, 68,
28–30, 38, 39, 42,
43, 49–53, 56, 57,
66, 75, 78, 79, 80,
13, 18, 19, 22, 23
14, 17, 40, 67, 90
(external)
Address
15, 41, 65, 91
A...A00
A...A01
A...A10
A...A11
First
QFP Pins
74, 24
70, 77
71, 76
95, 96
86
83
84
85
31
64
(internal)
Address
Second
A...A01
A...A00
A...A10
A...A11
DQ1–DQ16
(continued)
Pin Name
MODE
DQP1,
ADSP
ADSC
DQP2
V
V
ADV
V
V
OE
NC
ZZ
CCQ
SSQ
CC
SS
(internal)
Address
A...A10
A...A00
A...A01
A...A11
Third
Asynchronous
Synchronous
Synchronous
Synchronous
I/O Ground
I/O Supply
Ground
Supply
Output
Output
Input-
Input-
Input-
Input-
Static
Input-
Input/
Input/
Type
Input
–
CC
(internal)
Address
)
A...A10
A...A01
A...A00
Fourth
A...A11
Output Enable: This active LOW asynchronous input enables the data
output drivers.
Address Advance: This active LOW input is used to control the internal
burst counter. A HIGH on this pin generates wait cycle (no address
advance).
Address Status Processor: This active LOW input, along with CE being
LOW, causes a new external address to be registered and a Read cycle is
initiated using the new address.
Address Status Controller: This active LOW input causes device to be
deselected or selected along with new external address to be registered. A
Read or Write cycle is initiated depending upon Write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects
Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
Snooze: This active HIGH input puts the device in low power consumption
standby mode. For normal operation, this input has to be either LOW or NC
(No Connect).
Data Inputs/Outputs: Low Byte is DQ1–DQ8. High Byte is DQ9–DQ16.
Input data must meet set-up and hold times around the rising edge of CLK.
Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity
bit for DQ9–DQ16.
Power Supply: +3.3V –5% and +10%
Ground: GND.
Output Buffer Supply: +2.375 to 3.6V
Output Buffer Ground: GND
No Connect: These signals are not internally connected.
Burst Address Table (MODE = GND)
(external)
Address
A...A00
A...A01
A...A10
A...A11
First
Description
(internal)
Address
Second
A...A01
A...A10
A...A11
A...A00
(internal)
Address
A...A10
A...A11
A...A00
A...A01
Third
GVT7164B18
CY7C1297A/
Page 4 of 13
(internal)
Address
Fourth
A...A11
A...A00
A...A01
A...A10