gvt7164b18 Cypress Semiconductor Corporation., gvt7164b18 Datasheet
gvt7164b18
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gvt7164b18 Summary of contents
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... Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05204 Rev. *A 64K X 18 Synchronous Burst SRAM The CY7C1297A/GVT7164B18 SRAM integrates 65536 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...
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... The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. Document #: 38-05204 Rev. *A [1] UPPER BYTE WRITE D Q LOWER BYTE WRITE D Q ENABLE D Q Input Register Address Register CLR Binary Counter and Logic CY7C1297A/ GVT7164B18 DQ1-DQ16 DQP1 DQP2 Page ...
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... Chip Enable: This active LOW input is used to enable the device and to gate Synchronous ADSP. Input- Chip Enable: This active LOW input is used to enable the device. Synchronous Input- Chip Enable: This active HIGH input is used to enable the device. Synchronous CY7C1297A/ GVT7164B18 A10 CCQ ...
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... No Connect: These signals are not internally connected. Burst Address Table (MODE = GND First Fourth Address Address (external) (internal) A...A00 A...A11 A...A01 A...A10 A...A10 A...A01 A...A11 A...A00 CY7C1297A/ GVT7164B18 Description Second Third Fourth Address Address Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A10 A...A11 A...A00 A...A11 A...A00 A ...
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... X H Next CY7C1297A/ GVT7164B18 ADSC ADV WRITE OE CLK ...
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... Max.; CLK frequency = 0 CC Device deselected; all inputs < > Max CLK cycle time > t min. KC Test Conditions MHz 3.3V CC CY7C1297A/ GVT7164B18 Ambient [9] Temperature V CC 0°C to +70°C 3.3V 5%/+10% Min. Max. 2.0 V +0.3 CCQ –0.3 0.8 –2 2 < V –2 2 OUT CC 2 ...
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... ALL INPUT PULSES 3.0V 90% 10 1.5 ns (b) (c) Symbol t KQ [23] Description Min [24, 25] 3 [24, 25] [24, 25] 0 [24, 25] [27] 2.5 [27] 0.5 CY7C1297A/ GVT7164B18 Symbol TQFP Typ 200us Vcctyp 90% Vccmin 10% 1.5 ns (d) Typ. Max. 0.016 66 MHz 50 MHz 50 MHz -9 -10 -12 Max. Min. Max. Min ...
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... This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table. Document #: 38-05204 Rev. *A [23] Description Min. is less than t and t is less than t KQHZ KQLZ OEHZ CY7C1297A/ GVT7164B18 66 MHz 50 MHz 50 MHz -9 -10 -12 Max. Min. Max. Min. . ...
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... ADV# OE KQLZ DQ SINGLE READ Note: 28. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. Document #: 38-05204 Rev OEQ t OELZ Q(A1) Q(A2) Q(A2+1) CY7C1297A/ GVT7164B18 Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Q(A2+2) Page ...
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... Timing Diagrams (continued) [28] Write Timing CLK t S ADSP# ADSC ADDRESS A1 WEL#, WEH#, BWE# GW# CE# ADV# OE# t KQX DQ Q SINGLE WRITE Document #: 38-05204 Rev OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE CY7C1297A/ GVT7164B18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE D(A3+2) Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges D(A3) Q(A4) Q(A4+1) Q(A4+2) Single Write Burst Read CY7C1297A/ GVT7164B18 A5 Q(A4+3) D(A5) D(A5+1) Burst Write Page ...
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... Document #: 38-05204 Rev. *A Package Name Package Type A101 100-lead Thin Quad Flat Pack A101 100-lead Thin Quad Flat Pack A101 100-lead Thin Quad Flat Pack CY7C1297A/ GVT7164B18 Operating Range Commercial Commercial Commercial 51-85050-A Page ...
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... Document Title: CY7C1297A/GVT7164B18 64K × 18 Synchronous Burst SRAM Document Number: 38-05204 Issue REV. ECN NO. Date ** 112434 02/06/02 *A 123141 01/19/03 Document #: 38-05204 Rev. *A Orig. of Change KOM Change CY part number from CY7C1314A to CY7C1297A RBI Add Power up Requirements to Operating Conditions Information CY7C1297A/ GVT7164B18 Description of Change Page ...