mt58l512y36d Micron Semiconductor Products, mt58l512y36d Datasheet - Page 3

• Manufacturer Part Number: mt58l512y36d
• Description: 16mb 1 Meg X 18, 512k X 32/36 Pipelined, Dcd Syncburst Sram
• Manufacturer: Micron Semiconductor Products

a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can be
from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device,
BWa# controls DQas and DQPa; BWb# controls DQbs
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQas and DQPa; BWb# controls
DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
TQFP PIN ASSIGNMENT TABLE
NOTE: 1. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
GENERAL DESCRIPTION (continued)
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Burst operation can be initiated with either address
Address and write control are registered on-chip to
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
x18
NC
NC
NC
NC
NC
NC
V
V
V
V
V
V
NC
NC
V
V
DD
DD
DD
DD
S S
S S
S S
S S
NC/DQPc
Q
Q
Q
x32/x36
DQd
DQd
DQd
DQd
DQd
DQd
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
1
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
NC
NC
NC
MODE (LBO#)
V
DNU
DNU
SA1
SA0
V
V
V
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
DD
DD
S S
S S
NC/DQPd
Q
x32/x36
DQd
DQd
1
PIPELINED, DCD SYNCBURST SRAM
3
controls DQds and DQPd. GW# LOW causes all bytes to
be written. Parity bits are only available on the x18 and
x36 versions.
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penalizing
system performance.
+3.3V or +2.5V power supply, and all inputs and outputs
are TTL-compatible. Users can implement either a 3.3V
or 2.5V I/O for the +3.3V V
V
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
(www.micronsemi.com/en/products/sram/) for the lat-
est data sheet.
16Mb: 1 MEG x 18, 512K x 32/36
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
DD
This device incorporates an additional pipelined
Micron’s 16Mb SyncBurst SRAMs operate from a
Please
Micron Technology, Inc., reserves the right to change products or specifications without notice.
. The device is ideally suited for Pentium
DQPa
DQa
DQa
DQa
DQa
x18
NC
NC
NC
NC
NC
NC
V
V
V
DQa
DQa
DQa
DQa
V
refer
V
V
NC
V
V
DD
DD
ZZ
DD
DD
S S
S S
S S
S S
NC/DQPa
Q
Q
Q
x32/x36
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
to
1
the
DD
or a 2.5V I/O for the +2.5V
PIN #
100
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Micron
©2000, Micron Technology, Inc.
x18
NC
NC
NC
NC
SA
ADVANCE
OE# (G#)
ADSC#
ADSP#
BWE#
BWa#
BWb#
ADV#
V
GW#
CE2#
Web
CLK
CE2
CE#
V
V
V
SA
SA
SA
SA
DD
DD
S S
S S
NC/DQPb
Q
x32/x36
BWd#
BWc#
DQb
DQb
®
site
and
1