mt58l512y36d Micron Semiconductor Products, mt58l512y36d Datasheet - Page 24

• Manufacturer Part Number: mt58l512y36d
• Description: 16mb 1 Meg X 18, 512k X 32/36 Pipelined, Dcd Syncburst Sram
• Manufacturer: Micron Semiconductor Products

TEST DATA-OUT (TDO)
from the registers. The output is active depending upon
the current state of the TAP state machine. (See Figure 5.)
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any regis-
ter. (See Figure 6.)
PERFORMING A TAP RESET
five rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while the
SRAM is operating.
TDO comes up in a High-Z state.
TAP REGISTERS
pins and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
INSTRUCTION REGISTER
instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in
Figure 5. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
The TDO output pin is used to serially clock data-out
A RESET is performed by forcing TMS HIGH (V
At power-up, the TAP is reset internally to ensure that
Registers are connected between the TDI and TDO
Three-bit instructions can be serially loaded into the
TMS
TCK
TDI
*x = 49 for the x18 configuration, x = 68 for the x36 configuration.
TAP Controller Block Diagram
Selection
Circuitry
TAP CONTROLLER
DD
Boundary Scan Register*
) for
31
Identification Register
x
Figure 6
30
Instruction Register
.
29
.
Bypass Register
24
PIPELINED, DCD SYNCBURST SRAM
.
.
.
.
.
.
the two least significant bits are loaded with a binary
“01” pattern to allow for fault isolation of the board-
level serial test data path.
BYPASS REGISTER
registers, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that can
be placed between the TDI and TDO pins. This allows
data to be shifted through the SRAM with minimal
delay. The bypass register is set LOW (V
BYPASS instruction is executed.
BOUNDARY SCAN REGISTER
input and bidirectional pins on the SRAM. Several no
connect (NC) pins are also included in the scan register
to reserve pins for 9Mb and 18Mb Claymore SRAMs. The
x36 configuration has a 68-bit-long register, and the x18
configuration has a 49-bit-long register.
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the TDI
and TDO pins when the controller is moved to the Shift-
DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE
Z instructions can be used to capture the contents of the
I/O ring.
which the bits are connected. Each bit corresponds to
one of the bumps on the SRAM package. The MSB of the
16Mb: 1 MEG x 18, 512K x 32/36
2
2
2
1
1
1
When the TAP controller is in the Capture-IR state,
To save time when serially shifting data through
The boundary scan register is connected to all the
The boundary scan register is loaded with the con-
The Boundary Scan Order tables show the order in
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
0
0
0
Selection
Circuitry
TDO
©2000, Micron Technology, Inc.
ADVANCE
SS
) when the