mt58l512y36d Micron Semiconductor Products, mt58l512y36d Datasheet

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... Part Number Example: MT58L1MY18DT-7.5 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM ™ MT58L1MY18D, MT58V1MV18D, MT58L512Y32D, MT58V512V32D, MT58L512Y36D, MT58V512V36D 3.3V V I/O, Pipelined, Double-Cycle Deselect -6 -7.5 -10 NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). MT58L1MY18D GENERAL DESCRIPTION ...

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... CE2# OE# NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM ...

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... NC DQd 50 NOTE Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM controls DQds and DQPd. GW# LOW causes all bytes to be written ...

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... NOTE Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 ...

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... ADV# 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TYPE S A0 Input Synchronous Address Inputs: These inputs are registered and must S A1 meet the setup and hold times around the rising edge of CLK. ...

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... JEDEC-standard term for MODE. DQa Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with Output DQa pins; Byte “b” is associated with DQb pins. For the x32 and x36 versions, Byte “a” is associated with DQa pins; Byte “b” is DQb associated with DQb pins ...

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... SA0 DNU (LBO#) TOP VIEW *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM PIN LAYOUT (TOP VIEW) 165-PIN FBGA ...

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... CE2# 11H 11H OE#(G#) 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TYPE SA0 Input Synchronous Address Inputs: These inputs are registered and must SA1 meet the setup and hold times around the rising edge of CLK. ...

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... Do not alter input state while device is operating. DQa Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas; Output Byte “b” is associated with DQbs. For the x32 and x36 versions, Byte “a” is associated with DQas; Byte “b” is associated with DQbs; ...

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... Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TYPE Q Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and DD Operating Conditions for range ...

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... WRITE Byte “ a ” WRITE All Bytes WRITE All Bytes NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM THIRD ADDRESS (INTERNAL) X ...

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... ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 ...

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... OL curves are available upon request should never exceed V DD 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM *Stresses greater than those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device ...

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... MODE has an internal pull-up, and input leakage = ±10µA. 4. The load used for values. AC I/O curves are available upon request. 5. This parameter is sampled. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Q = +2.5V ±0.125V unless otherwise noted) DD CONDITIONS ...

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... Junction to Ambient Test conditions follow standard test methods (Airflow of 1m/s) Junction to Case (Top) Junction to Pins (Bottom) NOTE: 1. This parameter is sampled. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM CONDITIONS SYMBOL T = 25º MHz; ...

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... Typical values are measured at 3.3V, 25ºC, and 10ns cycle time. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM £ ...

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... This parameter is measured with the output loading shown in Figure 2. 4. This parameter is sampled. 5. Transition is measured ±500mV from steady state voltage. 6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these parameters “Don’t Care” when a byte write enable is sampled LOW. ...

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... SyncBurst SRAM timing is dependent upon the capaci- tive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 3.3V I/O Output Load Equivalents = (V /2 ...

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... I SUPPLY I ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH met ...

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... Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 ...

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... Full-width WRITE can be initiated by GW# LOW GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device; or GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 ...

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... The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM ...

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... NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TEST ACCESS PORT (TAP) TEST CLOCK (TCK) The test clock is used only with the TAP controller ...

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... DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the 0 Bypass Register 2 1 ...

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... PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM ...

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... CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 7. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM ...

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... V Power-up During normal operation pulse widths less than KHKL (MIN) or operate at frequencies exceeding 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM to 2. £ +2.6V unless otherwise noted) CONDITIONS ...

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... Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Do Not Use: This instruction is reserved for future use. ...

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... DQPa ADV# 22 ADSP 23 ADSC# 24 OE# (G#) 25 BWE# 26 GW# 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM PIN ID FBGA BIT# TBD 27 TBD 28 TBD 29 TBD 30 TBD 31 TBD 32 TBD 33 TBD ...

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... NC/DQPb ADV# 30 ADSP# 31 ADSC# 32 OE# (G#) 33 BWE# 34 GW# 35 CLK 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM PIN ID FBGA BIT# TBD 36 TBD 37 TBD 38 TBD 39 TBD 40 TBD 41 TBD 42 TBD ...

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... QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 ...

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... NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM ...

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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 SyncBurst is a trademark and Micron is a registered trademark of Micron Technology, Inc. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 ...

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... Added note: ZZ has internal pull-down Updated Boundary Scan Order, Rev. 3/00, ADVANCE ..................................................................................... Apr/6/00 Added ADVANCE status, Rev. 1/00, ADVANCE .............................................................................................. Jan/18/00 MT58L1MY18D, Rev. 11/99, ADVANCE........................................................................................................ Nov/11/99 Added BGA JTAG functionality 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 34 Micron Technology, Inc ...