hdmp-1526 ETC-unknow, hdmp-1526 Datasheet - Page 4

• Manufacturer Part Number: hdmp-1526
• Description: Fibre Channel Transceiver Chip
• Manufacturer: ETC-unknow

 
HDMP-1526 (Transmitter Section)
Timing Characteristics
T
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the
rising edge of the first bit transmitted).
Figure 3. Transmitter Section Timing.
Figure 4. Transmitter Latency.
C
TX[0]-TX[9]
TX[0]-TX[9]
= 0 C to +85 C, V
REFCLK
REFCLK
± DOUT
t_txlat
Symbol
t




t
setup

hold
[1]
T5
T6


 
T7
DATA
CC
T8
= 4.5 V to 5.25 V
Setup Time
Hold Time
Transmitter Latency
t-SETUP

T9
Parameter
T0
D ATA
T1

 

T2
DATA BYTE B
t-HOLD
T3
DATA BYTE A




T4
DATA
T5
t_TXLAT
T6


 
Units
nsec
nsec
nsec
bits
T7
DATA
T8

 
T9
T0
Min.
1.5
2
T1
DATA
DATA BYTE B
DATA BYTE C
T2
T3
Typ.
6.25
6.64
T4
T5
1.4 V
2.0 V
0.8 V
1.4 V
Max.
12.2
13.0
685