hdmp-1526 ETC-unknow, hdmp-1526 Datasheet - Page 2

• Manufacturer Part Number: hdmp-1526
• Description: Fibre Channel Transceiver Chip
• Manufacturer: ETC-unknow

Figure 1. Typical Application Using the HDMP-1526.
Figure 2. HDMP-1526 Transceiver Block Diagram.
DATA BYTE
DATA BYTE
ENBYTSYNC
-LCKREF
REFCLK
RXCAP0
RXCAP1
TXCAP0
TXCAP1
RX[0-9]
TX[0-9]
-LCKREF
RBC0
RBC1
REFCLK
PROTOCOL DEVICE
GENERATOR
PLL/CLOCK
BYTSYNC
BYTSYNC
TX
BYTE SYNC
FRAME
FRAME
DEMUX
MUX
AND
ENBYTSYNC
INTERNAL
Tx CLOCKS
TRANSMITTER SECTION
RECEIVER SECTION
PLL
SAMPLER
PLL/CLOCK
RECOVERY
INPUT
HDMP-1526
RX
Rx CLOCKS
INTERNAL
LOOPBACK
INTERNAL
PLL
OUTPUT
SELECT
SELECT
INPUT
SERIAL DATA OUT
SERIAL DATA IN
LOOPEN
± DOUT
± DIN
HDMP-1526 Block Diagram
The HDMP-1526 was designed to
transmit and receive 10-bit wide
parallel data over a single high-
speed line, as specified for the FC-0
layer of the Fibre Channel standard.
The parallel data applied to the
transmitter is expected to be
encoded per the Fibre Channel
specification, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order to
accomplish this task, the HDMP-
1526 incorporates the following:
• TTL Parallel I/Os
• High-Speed Phase Lock Loops
• Clock Generation/Recovery
• Parallel-to-Serial Converter
• High-Speed Serial Clock-and-Data
• Comma Character Recognition
• Byte Alignment Circuitry
• Serial-to-Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit wide
TTL parallel data at inputs TX[0..9].
The user-provided reference clock
signal, REFCLK, is also used as the
transmit byte clock. The TX[0..9]
and REFCLK signals must be
properly aligned, as shown in
Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based on
the supplied reference byte clock
(REFCLK). REFCLK is used as both
the frequency reference clock for
the PLL and the transmit byte clock
for the incoming data latches. It is
expected to be 106.25 MHz and
properly aligned to the incoming
Circuitry
Recovery Circuitry
Circuitry
683