ppc440epx-nta667t ETC-unknow, ppc440epx-nta667t Datasheet - Page 86

• Manufacturer Part Number: ppc440epx-nta667t
• Description: Mpu 440epx Risc 32-bit 0.13um 667mhz 1.8v/2.5v/3.3v 680-pin Tebga Tray
• Manufacturer: ETC-unknow

440EPx – PPC440EPx Embedded Processor
Figure 10. DDR SDRAM Write Cycle Timing
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 25. I/O Timing—DDR SDRAM T
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 166MHz.
86
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
Signal Name
MemClkOut
T
T
T
T
T
T
SK
SA
SD
HD
HA
DS
MemData
PLB Clk
= Delay from falling edge of MemClkOut to rising/falling edge of signal (skew)
= Setup time for address and command
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Hold time for address and command signals from MemClkOut
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
DQS
Addr/Cmd
DS
T
SA
T
SK
T
HA
Minimum
−0.030
−0.030
−0.050
−0.110
−0.140
−0.120
−0.060
−0.010
−0.140
T
T
SD
DS
T
HD
T
DS
T
DS
(ns)
T
Revision 1.30 – February 27, 2009
SD
T
HD
Maximum
+0.650
+0.620
+0.580
+0.480
+0.410
+0.480
+0.580
+0.690
+0.420
Data Sheet
AMCC Proprietary