ppc440epx-nta667t ETC-unknow, ppc440epx-nta667t Datasheet - Page 5

• Manufacturer Part Number: ppc440epx-nta667t
• Description: Mpu 440epx Risc 32-bit 0.13um 667mhz 1.8v/2.5v/3.3v 680-pin Tebga Tray
• Manufacturer: ETC-unknow

Revision 1.30 – February 27, 2009
Block Diagram
Figure 2. PPC440EPx Functional Block Diagram
The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect Bus
Address Maps
The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map.
This address map defines the possible contents of various address regions which the processor can access. The
second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440EPx processor through the use of mtdcr and mfdcr instructions.
AMCC Proprietary
Data Sheet
333MHz max
data rate
- 14-bit addr
- 64/32-bit data
Interrupts
External
UIC
FPU
10
(optional)
Security
Controller
DDR2/1
SDRAM
Control,
Reset
Clock
Controller
D-Cache
PLB (PLB4—128 bits)
DMA
32KB
JTAG
OPB 1
Device
Processor
PPC440
USB 2.0
Timers
MMU
2.0 PHY
Bridge
OPB
D+/D−
I-Cache
Host
32KB
Trace
Power
Bridge
Mgmt
OPB
1 host 2.0 PHY
1 Device UTMI
or
1 Device 2.0 PHY
OPB 2
SRAM
16KB
Bridge
OPB
MAL
DCR Bus
DCRs
PLB-PLB
Bridges
10/100/1000
ZMII
440EPx – PPC440EPx Embedded Processor
Ethernet
83MHz max
x2
- 30-bit addr
- 32/16-bit data
RGMII
On-chip Peripheral Bus (OPB 0)
Peripheral
Controller
External
Bridge
GPIO
OPB
PLB (PLB3—64 bits)
™
Architecture.
SPI
Controller
NAND
Controller
Flash
DMA
IIC
x2
Bridge
PCI
BSC
GPT
66MHz max
- 32 bits
- 6 devices
UART
x4
5