mt18hvf25672py-53e Micron Semiconductor Products, mt18hvf25672py-53e Datasheet - Page 4

• Manufacturer Part Number: mt18hvf25672py-53e
• Description: 1gb, 2gb X72, Ecc, Sr 240-pin Ddr2 Vlp Rdimm
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef827840fc/Source: 09005aef826fd98c
HVF18C128_256x72.fm - Rev. A 3/07 EN
DQS0#–DQS17#
BA0, BA1, BA2
DQS0–DQS17,
RAS#, CAS#,
DQ0–DQ63
CK0, CK0#
V
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
E
A0–A13
RESET#
DD
V
P
RR
ODT0
(1GB)
(2GB)
CKE0
WE#
AR
SDA
V
DDSPD
RFU
S0#
SCL
V
NC
/V
_O
REF
SS
_I
DD
N
UT
Q
Pin Descriptions
(open drain)
(LVCMOS)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Output
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
–
On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#,
and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
Chip select: S# (registered LOW) enables and disables (registered HIGH) the command
decoder.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode register,
including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Parity bit for the address and control bus.
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
Presence-detect address inputs: These pins are used to configure the presence-detect
device.
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be
used during power up to ensure that CKE is LOW and DQs are High-Z.
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
Data input/output: Bidirectional data bus.
Check bits.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
Parity error found on the address and control bus.
Power supply: 1.8V ±0.1V.
SSTL_18 reference voltage.
Ground.
Serial EEPROM positive power supply: +1.7V to +3.6V.
No connect: These pins should be left unconnected.
Reserved for future use.
1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
4
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2007 Micron Technology, Inc. All rights reserved.