th50vsf3681aasb TOSHIBA Semiconductor CORPORATION, th50vsf3681aasb Datasheet - Page 35

• Manufacturer Part Number: th50vsf3681aasb
• Description: Sram Flash Memory Mixed Multi-chip Package
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DQ3 (Block Erase timer)
cycle. DQ3 outputs a 0 during the Block Erase Hold Time and a 1 when the Erase operation starts. Additional
Block Erase commands can only be accepted during this Block Erase Hold Time. Each Block Erase command
received within this hold time resets the timer, allowing additional blocks to be marked for erasing. DQ3 outputs
a 1 if the Program or Erase operation fails.
DQ2 (Toggle bit 2)
time 1 is output from non-selected blocks; thus, the selected block can be detected. When the device is in Erase
Suspend mode, if data are continuously read from the selected block for Auto Block Erase, DQ2 output toggles. At
this time, because DQ6 output does not toggle, Erase Suspend mode can be detected. When the device is in
Programming mode during Erase suspend, if data are read from the address to which data are being written,
DQ2 outputs 1.
(Busy state) indicates that an Auto Program or Auto Erase operation is in progress. A 1 (Ready state) indicates
that the operation has finished and that the device can accept a new command. The
when an operation has failed.
outputs a 1 during an Erase Suspend operation. The output buffer for the
circuit, allowing a wired  OR connection. A pull-up resistor needs to be inserted between V
pin.
RY
The Block Erase operation starts 50 µs (Erase Hold Time) after the rising edge of WE in the last command
DQ2 is used to detect blocks for Auto Block Erase or to detect whether the device is in Erase Suspend mode.
During Auto Block Erase, if data are continuously read from the selected block, DQ2 output toggles. At this
The TH50VSF3680/3681AASB has a
The
During an Auto Block Erase operation, commands other than Erase Suspend are ignored. The
/
BY
RY
(READY /
/
BY
signal outputs a 0 after the rising edge of WE in the last command cycle.
BUSY
)
RY
/
BY
signal to indicate the device status to the host processor. A 0
TH50VSF3680/3681AASB
RY
/
BY
RY
pin is an open drain type
2001-03-06 35/55
/
BY
CC
signal outputs a 0
and the
RY
/
BY
RY
signal
/
BY