am42dl3224gt71it Meet Spansion Inc., am42dl3224gt71it Datasheet
am42dl3224gt71it
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am42dl3224gt71it Summary of contents
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PRELIMINARY Am42DL32x4G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power ...
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GENERAL DESCRIPTION Am29DL32xG Features The Am29DL322G/323G/324G consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram ...
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Figure 33. CE1#s Controlled Data Retention Mode........................ 61 Figure 34. CE2s Controlled Data Retention Mode.......................... 61 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Speed Range Options 71 2.7–3.3 V Max Access Time (ns) 70 CE# Access (ns) 70 OE# Access (ns) 30 MCP BLOCK DIAGRAM A20 to A0 A20 to A0 A–1 WP#/ACC ...
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FLASH MEMORY BLOCK DIAGRAM A20–A0 RY/BY# A20–A0 RESET# STATE CONTROL WE# & CE# COMMAND CIOf REGISTER WP#/ACC DQ15–DQ0 A20– Upper Bank Address Upper Bank ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 ...
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PIN DESCRIPTION A17– Address Inputs (Common) A-1, A20–A18 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am42DL32x AMD DEVICE NUMBER/DESCRIPTION Am42DL32x4G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL32xG 32 Megabit ( 8-Bit 16-Bit) CMOS ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- t ion. The reg ister is ...
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Table 1. Device Bus Operations—Flash Word Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash Standby 0 Output Disable ...
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Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash Standby ...
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Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ15–DQ0 are active and controlled ...
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Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance ...
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Sector Address Sector SA0 000000xxx SA1 000001xxx SA2 000010xxx SA3 SA4 000100xxx SA5 000101xxx SA6 SA7 SA8 001000xxx SA9 001001xxx SA10 001010xxx SA11 SA12 SA13 SA14 SA15 SA16 010000xxx SA17 010001xxx SA18 010010xxx SA19 SA20 010100xxx SA21 010101xxx SA22 SA23 ...
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Table 4. Top Boot Sector Addresses (Continued) Sector Address Sector SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Note: The address range is A20:A-1 in ...
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Sector Address Sector SA0 000000000 SA1 000000001 SA2 000000010 SA3 000000011 SA4 000000100 SA5 000000101 SA6 000000110 SA7 000000111 SA8 000001xxx SA9 000010xxx SA10 SA11 000100xxx SA12 000101xxx SA13 SA14 SA15 001000xxx SA16 001001xxx SA17 001010xxx SA18 SA19 SA20 SA21 ...
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Table 6. Bottom Boot Sector Addresses (Continued) Sector Address Sector SA39 100000xxx SA40 100001xxx SA41 100010xxx SA42 SA43 100100xxx SA44 100101xxx SA45 SA46 SA47 101000xxx SA48 101001xxx SA49 101010xxx SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip ...
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Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A20–A12 SA70 111111XXX 111110XXX, SA69-SA67 111101XXX, 111100XXX SA66-SA63 1110XXXXX SA62-SA59 1101XXXXX SA58-SA55 1100XXXXX SA54-SA51 1011XXXXX SA50-SA47 1010XXXXX SA46-SA43 1001XXXXX SA42-SA39 1000XXXXX SA38-SA35 0111XXXXX SA34-SA31 0110XXXXX SA30-SA27 0101XXXXX SA26-SA23 0100XXXXX SA22–SA19 ...
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START RESET (Note 1) Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector uses a SecSi Sector Indica- tor Bit to ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 14 and 16 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Tables 14 and 16 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper ...
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Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Tables 14 and 16 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence ...
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Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# ...
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Table 14. Command Definitions (Flash Word Mode) Command First Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Manufacturer ID 4 555 Device ID 4 555 SecSi Sector Factory 4 555 Protect (Note 9) Sector ...
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Table 16. Command Definitions (Flash Byte Mode) Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID 6 SecSi Sector Factory Protect 4 (Note 9) Sector Protect Verify 4 (Note 10) Enter ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18 and the following subsec- tions describe the function of these bits. DQ7 and ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +125 C Ambient Temperature with Power Applied . . . . . . . . ...
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DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V Active Read Current CC1 (Notes ...
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SRAM DC AND OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current Average Operating Current CC1 I s Average Operating Current CC2 V Input Low ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6 Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 2.0 V 1.0 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating Between SRAM to Flash ...
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AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Flash Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t /t CE#f to CIOf Switching Low or High ELFL ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching High to Output Active FHQV CE#f OE# ...
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AC CHARACTERISTICS Flash Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to OE ASO Polling t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address program data Illustration shows ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes sector address (for Sector Erase), ...
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AC CHARACTERISTICS t WC Addresses Valid CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t CE ...
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AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary t RSP Sector/Sector Block Unprotect ...
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AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, A6 ...
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AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to CE#f Low During Toggle ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS SRAM Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip Enable to Output CO1 CO2 t Output Enable Access Time OE t LB#s, UB#s to Access Time BA ...
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AC CHARACTERISTICS Address CE#1s CE2s OE# Data Out High-Z Notes WE# remains high for the read cycle and t are defined as the time at which the outputs achieve the open circuit ...
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AC CHARACTERISTICS SRAM Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of Write AW t UB#s, LB#s to End of ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled measured from CE1#s going low to the end of write measured from the end of write to ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In (See Note 6) Data Out Notes: 1. UB#s and LB#s controlled measured from CE1#s going low to the end of write measured from ...
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Flash Erase And Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Accelerated Byte/Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the ...
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SRAM DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t Data Retention Set-Up Time SDR t Recovery Time RDR Notes: 1. CE1#s V – 0.2 V, CE2s V – 0.2 ...
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PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array Am42DL32x4G May 19, 2003 ...
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REVISION SUMMARY Revision A (January 9, 2002) Initial release. Revision (September 30, 2002) Connection Diagram Changed H7 from NC to DQ13. Logic Symbol Changed from address inputs for A17 to A0. Sector/Sector Block Protection ...
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