ia186xl Innovasic Semiconductor Inc., ia186xl Datasheet - Page 25

no-image

ia186xl

Manufacturer Part Number
ia186xl
Description
16-bit Microcontroller
Manufacturer
Innovasic Semiconductor Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ia186xlPLC68IR1
Manufacturer:
INNOVASIC
Quantity:
20 000
Part Number:
ia186xlPLC68IR2
Manufacturer:
Innovasic Semiconductor
Quantity:
10 000
Part Number:
ia186xlPLC68IR2/1/0
Manufacturer:
INNOVAS
Quantity:
3 396
IA186XL/IA188XL
16-Bit Microcontrollers
Table 7. IA186XL Pin/Signal Descriptions (Continued)
ale
ardy
bhe_n
busy
clkout
den_n
drq0
drq1
Signal
test_n/busy
ale/qs0
bhe_n
den_n
Name
clkout
drq0
drq1
ardy
®
PLCC
61
55
64
47
56
39
18
19
Pin
UNCONTROLLED WHEN PRINTED OR COPIED
PQFP
10
20
29
19
38
61
60
7
ENG211080711-01
Page 25 of 72
LQFP
29
37
26
46
36
56
79
78
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
asynchronous ready tells the processor the
addressed memory space or i/o device will
complete the transfer.
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
Additionally, bhe_n and ad0 encode the
following bus information:
ad0
Note: bhe_n is multiplexed with refresh_n.
busy. Input. Active High. When the busy
input is asserted, it causes the IA186XL to
suspend operation during the execution of the
Intel 80C187 Numerics Coprocessor
instructions. Operation resumes when the pin
is sampled low.
clock output. Output. The clkout pin
provides a timing reference for inputs and
outputs of the IA186XL. This clock output is
one-half the input clock (clkin) frequency.
The clkout signal has a 50% duty cycle,
transitioning every falling edge of clkin.
data enable. Output. Active Low. This signal
is used to enable of bidirectional transceivers
in a buffered system. The den_n signal is
asserted (low) only when data are to be
transferred on the bus.
dma request0 or 1 is asserted high by an
external device when ready for DMA Channel
0 or 1 to perform a transfer. These signals are
level-triggered and internally synchronized
0
0
1
1
bhe_n Bus Status
0
1
0
1
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
Description
Preliminary Data Sheet
September 30, 2008
http://www.Innovasic.com
Customer Support:
1-888-824-4184

Related parts for ia186xl