ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 35

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

In non-enhanced mode, this bit enables the CTS/RTS out-
of-band flow control.
MCR[6]: IrDA mode
logic 0
logic 1
This function is only available in Enhanced mode. It
requires a 16x clock to function correctly.
MCR[7]: Baud rate prescaler select
logic 0
logic 1
Where M & N are programmed in CPR (ICR offset 0x01).
After a hardware reset, CPR defaults to 0x20 (divide-by-4)
and MCR[7] is reset to ‘0’. User writes to this flag will only
take effect in enhanced mode. See section 6.9.1.
6.7.2
MSR[0]: Delta CTS#
Indicates that the CTS# input has changed since the last
time the MSR was read.
MSR[1]: Delta DSR#
6.8
6.8.1
The divisor latch registers are used to program the baud
rate divisor. This is a value between 1 and 65535 by which
the input clock is divided by in order to generate serial
baud rates. After a hardware reset, the baud rate used by
the transmitter and receiver is given by:
Where divisor is given by DLL + ( 256 x DLM ). More
flexible baud rate generation options are also available.
See section 6.10 for full details.
6.9
Automatic in-band flow control, automatic out - of - band flow
control and special character detection features can be
used when in Enhanced mode and are software compatible
with the 16C654. Alternatively, 16C750 compatible
automatic out - of - band flow control can be enabled when in
non-Enhanced mode. In 950 mode, in-band and out - of-
OXFORD SEMICONDUCTOR LTD.
Other Standard Registers
Automatic Flow Control
Modem Status Register ‘MSR’
Divisor Latch Registers ‘DLL & DLM’
Baudrate
Standard serial receiver and transmitter data
format.
Data will be transmitted and received in IrDA
format.
Normal (divide by 1) baud rate generator
prescaler selected.
Divide-by-“M N/8” baud rate generator
prescaler selected.
16
InputClock
*
Divisor
Indicates that the DSR# input has changed since the last
time the MSR was read.
MSR[2]: Trailing edge RI#
Indicates that the RI# input has changed from low to high
since the last time the MSR was read.
MSR[3]: Delta DCD#
Indicates that the DCD# input has changed since the last
time the MSR was read.
MSR[4]: CTS
This bit is the complement of the CTS# input. It is
equivalent to RTS (MCR[1]) during internal loop-back
mode.
MSR[5]: DSR
This bit is the complement of the DSR# input. It is
equivalent to DTR (MCR[0]) during internal loop-back
mode.
MSR[6]: RI
This bit is the complement of the RI# input. In internal loop-
back mode it is equivalent to the internal OUT1.
MSR[7]: DCD
This bit is the complement of the DCD# input. In internal
loop-back mode it is equivalent to the internal OUT2.
6.8.2
The scratch pad register does not affect operation of the
rest of the UART in any way and can be used for
temporary data storage. The register may also be used to
define an offset value to access the registers in the
Indexed Control Register set. For more information on
Indexed Control registers see Table 24 and section 6.11.
band flow controls are compatible with 16C654, with the
addition of fully programmable flow control thresholds.
6.9.1
Writing 0xBF to LCR enables access to the EFR and other
Enhanced mode registers. This value corresponds to an
Scratch Pad Register ‘SPR’
Enhanced Features Register ‘EFR’
OXCF950 DATA SHEET V1.1
Page 35