ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 15

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

Divide Value field in the DIV local configuration register (see section 6.3.4.3). This allows the length of the pulse to be varied, so
that different clock frequencies can be used and the pulse can still be kept as short as possible, without violating the minimum
length of 50 s as defined in the PCMCIA Standard. Table 12 shows how the register should be programmed for different clock
frequencies.
5.4.2
The OXCF950 has three possible interrupt sources. These are the internal UART, and the two multi-purpose I/O pins, which can
be configured as interrupts using the MIO Configuration Register (MIC – see section 6.3.4.2) and the Interrupt Status and Control
Register (ISR – see section 6.3.4.5)
When the OXCF950 is requesting interrupt service, the Intr field within the Configuration Status Register (CSR – see section
6.5.2) will be set to 1. Otherwise this field will be cleared to 0. The Intr field value is controlled by the interrupt source (i.e UART
or MIO [1:0]). The status of the actual interrupts can be read from the ISR register.
5.5
Each PCMCIA/CF card’s I/O function must implement Function Configuration Registers (FCR). These registers allow the host to
configure the function provided by the card, and are mapped into the attribute memory space at the location specified within the
CONFIG tuple (in the CIS). The CONFIG tuple defines a base address for the Function Configuration Registers and a number
corresponding to how may registers are supported (4 regist e rs in the OXCF950). Each of these registers has read/write
capability and is mapped at even location, consistent with the design of attribute memory. The registers supported in the
OXCF950 are shown in the following table.
Offset from
FCR base
address
0
2
4
8
Due to the type of function the OXCF950 configures the card to be, and the fact that it is a single function device, only a sub-set
of the total number of configuration registers are required.
The definition of each configuration register is detailed in the next few sub- sections.
OXFORD SEMICONDUCTOR LTD.
CF/PCMCIA Function Configuration Registers
Interrupt Sources
Attribute
memory address
F8
FA
FC
FE
16
32
2
4
8
Clock Frequency (MHz)
Register
Configuration Options Register
Configuration and Status Register
Pin Replacement Register
Socket & Copy Register
Table 12: Interrupt Pulse Divide Value settings
<=
<=
<=
<=
<=
Table 13: Configuration Register Mapping
RESERVED
f
f
f
f
f
f
<
<
<
<
<
<
16
32
64
2
4
8
Interrupt Divider Setting
000
001
010
011
100
101
110
111
OXCF950 DATA SHEET V1.1
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