ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 28

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

6.3
6.3.1
After a hardware reset or soft reset (bit 7 of COR register),
all writable registers are reset to 0x00, with the following
exceptions:
1. DLL which is reset to 0x01.
2. CPR is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 0000000
TFL[6:0]: 0000000
LSR[7:0]: 0x60 signifying that both the transmitter and the
MSR[3:0]: 0000
MSR[7:4]: Dependent on modem input lines DCD, RI, DSR
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx00000
RFC[7:0]: 00000000
GDS[7:0]: 00000001
6.4
Both the transmitter and receiver have associated holding
registers (FIFOs), referred to as the transmitter holding
register (THR) and receiver holding register (RHR)
respectively.
In normal operation, when the transmitter finishes
transmitting a byte it will remove the next dat a from the top
of the THR and proceed to transmit it. If the THR is empty,
it will wait until data is written into it. If THR is empty and
the last character being transmitted has been completed
(i.e. the transmitter shift register is empty) the transmitter is
said to be idle. Similarly, when the receiver finishes
receiving a byte, it will transfer it to the bottom of the RHR.
If the RHR is full, an overrun condition will occur (see
section 6.5.3).
OXFORD SEMICONDUCTOR LTD.
Reset Configuration
Transmitter & Receiver FIFOs
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 111
Write the desired value to ICR (address 101
Reading from ICR registers:
Ensure that the last value written to LCR was not 0xBF (see above).
Write 0x00 offset to SPR to select ACR.
Set bit 6 of ACR (ICR read enable) by writing x1xxxxxx
(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!)
Write the desired offset to SPR (address 111
Read the desired value from ICR (address 101
Write 0x00 offset to SPR to select ACR.
Clear bit 6 of ACR bye writing x0xxxxxx
Host Reset
transmitter FIFO are empty
and CTS respectively
2
2
2
2
2
2
2
to ICR, thus enabling access to standard registers again.
2
).
2
2
).
).
2
).
2
to address 101
DMS[7:0]: 00000010
CKA[7:0]: 00000000
The reset state of output signals for are tabulated below:
6.3.2
An additional feature available in the 950 core is software
resetting of the serial channel. The software reset is
available using the CSR register. Software reset has t h e
same effect as a hardware reset except it does not reset
the clock source selections (i.e. CKS register and CKA
register). To reset the UART write 0x00 to the Channel
Software Reset register ‘CSR’.
Data is written into the bottom of the THR queue and read
from the top of the RHR queue completely asynchronously
to the operation of the transmitter and receiver.
The size of the FIFOs is dependent on the setting of the
FCR register. When in Byte mode, these FIFOs only
accept one by te at a time before indicating that they are
full; this is compatible with the 16C450. When in a FIFO
mode, the size of the FIFOs is either 16 (compatible with
the 16C550) or 128.
Data written to the THR when it is full is lost. Data read
from the RHR when it is empty is invalid. The empty or full
status of the FIFOs are indicated in the Line Status
Signal
SOUT
DTR#
RTS#
2
. Ensure that other bits in ACR are not changed.
Software Reset
Table 25: Output Signal Reset State
OXCF950 DATA SHEET V1.1
2
2
Inactive High
Inactive High
Inactive High
Reset state
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