71m6545h-igtr/f Maxim Integrated Products, Inc., 71m6545h-igtr/f Datasheet - Page 93

• Manufacturer Part Number: 71m6545h-igtr/f
• Description: Metrology Processors
• Manufacturer: Maxim Integrated Products, Inc.

PDS_6545_009
v1.0
Name
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
MUX_DIV[3:0]
Reserved
Reserved
DIO55_EN
Reserved
Reserved
OSC_COMP
PB_STATE
PERR_RD
PERR_WR
PLL_OK
PLL_FAST
PLS_MAXWIDTH[7:0]
SFR FC[6]
SFR FC[5]
SFR F8[0]
SFR F9[4]
210A[7:0]
Location
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:4]
2101[3:0]
2101[7:4]
2100[3:0]
2100[7:4]
2457[5:4]
2456[3:0]
28A0[5]
2457[0]
2457[2]
2457[1]
2200[4]
0000 –
Rst Wk Dir
00
FF FF R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
© 2008–2011 Teridian Semiconductor Corporation
Description
Selects which ADC input is to be converted during time slot 2.
Selects which ADC input is to be converted during time slot 3.
Selects which ADC input is to be converted during time slot 4.
Selects which ADC input is to be converted during time slot 5.
Selects which ADC input is to be converted during time slot 6.
Selects which ADC input is to be converted during time slot 7.
Selects which ADC input is to be converted during time slot 8.
Selects which ADC input is to be converted during time slot 9.
Selects which ADC input is to be converted during time slot 10.
MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The maximum
number of time slots is 11.
Reserved. Must be 0.
Reserved. Must be 00.
Enables DIO55
DIO55_EN = 0: DIO55 is disabled
DIO55_EN = 1: DIO55 is enabled
Reserved. Must be 0.
Reserved. Must be 0000.
Enables the automatic update of RTC_P[16:0] and RTC_Q [1:0]every time the
temperature is measured.
The de-bounced state of the PB pin.
The 71M6545/H sets these bits to indicate that a parity error on the remote sensor has
been detected. Once set, the bits are remembered until they are cleared by the MPU.
Indicates that the clock generation PLL is settled.
Controls the speed of the PLL and MCK.
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
Determines the maximum width of the pulse (low-going pulse).
Maximum pulse width is (2*PLS_MAXWIDTH + 1)*T
PLS_INTERVAL = 0 or PLS_MAXWIDTH=255, no width checking is performed and the
output pulses have 50% duty cycle.
I
. Where T
I
is PLS_INTERVAL. If
Data Sheet 71M6545/H
93