71m6545h-igtr/f Maxim Integrated Products, Inc., 71m6545h-igtr/f Datasheet - Page 55

• Manufacturer Part Number: 71m6545h-igtr/f
• Description: Metrology Processors
• Manufacturer: Maxim Integrated Products, Inc.

DIO pins can be configured independently as an input or output. For DIO0 to DIO14, this is done with the
PDS_6545_009
See
STEMP[10:0] information from the 71M6xx3.
2.5.7 71M6545/H Battery Monitor
The 71M6545/H temperature measurement circuit can also monitor the battery at the VBAT_RTC pin.
When TEMP_BAT (I/O RAM 0x28A0[4]) is set, a battery measurement is performed as part of each
temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM
0x2885). The following equations are used to calculate the voltage measured on the VBAT_RTC pin from
the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts. In MSN mode,
TEMP_PWR = 1 use:
In MSN mode, a 100 µA de-passivation load can be applied to the battery by setting the BCURR (I/O RAM
0x2704[3]) bit. Battery impedance can be measured by taking a battery measurement with and without
BCURR. Regardless of the BCURR bit setting, the battery load is never applied in SLP mode.
2.5.8 71M6xx3 VCC Monitor
The 71M6xx3 monitors its VCC pin voltage. The voltage of the VCC pin can be obtained by the 71M6545/H
by issuing a read command to the 71M6xx3. The 71M6545/H must request both the VSENSE[7:0] and
STEMP[10:0] values from the 71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate the
71M6xx3 VCC pin voltage from the VSENSE[7:0] and STEMP[10:0] values read from the 71M6xx3.
See
VSENSE[7:0] and STEMP[10:0] from the 71M6xx3 remote sensors.
2.5.9 UART Interface
The 71M6545/H provides an asynchronous interface (UART). The UART can be used to connect to AMR
modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash memory.
2.5.10 DIO Pins
On reset or power-up, all DIO pins are DIO inputs until they are configured for the desired configuration under
MPU control.
SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3 (SFR 0xB0) as shown in
Example: DIO12 (pin 19, gray fields in
by writing 1 to both P3[4]and P3[0].
The configuration for pins DIO19 to DIO25, DIO28 and DIO29 are shown in
The configuration for pins DIO55 is shown in
v1.0
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
2.2.8.3 Control of the 71M6xx3 Isolated Sensor
2.2.8.3 Control of the 71M6xx3 Isolated Sensor
Pin #
After reset or power up, pins DIO0 through DIO14 are initially DIO outputs, but are disabled by
PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses. After configuring pins DIO0 through
DIO14 the host enables the pins by setting PORT_E = 1.
DIO
Table 44: Data/Direction Registers and Internal Resources for DIO0 to DIO14
VBAT
31
_
0
4
--
0
© 2008–2011 Teridian Semiconductor Corporation
RTC
P0 (SFR80)
P0 (SFR80)
30
1
--
1
5
=
3
3 .
29
--
2
6
2
V
Table
+
(
28
BSENSE
3
7
--
3
44) is configured as a DIO output pin with a value of 1 (high)
Table
27
4
0
4
Y
P1 (SFR90)
P1 (SFR90)
−
46.
142
26
on page
Y
on page
5
1
5
)
⋅
. 0
25
Y
6
2
6
0246
22
22
24
Y
V
7
3
7
for information on how to read
for information on how to read the
+
STEMP
23
Y
0
4
8
P2 (SFRA0)
P2 (SFRA0)
22
Y
9
1
5
⋅
. 0
Table 45
000297
10
21
Y
2
6
Data Sheet 71M6545/H
V
11
20
Y
3
7
12
19
Table
0
4
–
P3 (SFRB0)
P3 (SFRB0)
13
18
1
5
–
44.
14
17
2
6
–
55