p89lpc932ba NXP Semiconductors, p89lpc932ba Datasheet - Page 35

• Manufacturer Part Number: p89lpc932ba
• Description: P89lpc932 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb Flash With 512-byte Data Eeprom And 768-byte Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12379
Product data
Fig 15. SPI block diagram.
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
8.21 Serial Peripheral Interface (SPI)
The P89LPC932 provides another high-speed serial communication interface—the
SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with
two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be
supported in either Master or Slave mode. It has a Transfer Completion Flag and
Write Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
Typical connections are shown in Figures
•
•
interrupt
request
SPI clock (master)
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and
flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal
is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port
functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave
device uses its SS pin to determine whether it is selected.
SPI
MSTR
SPEN
Rev. 04 — 06 January 2004
internal
data
bus
8-bit microcontroller with accelerated two-clock 80C51 core
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
clock
16
through 18.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
M
M
M
S
S
S
P89LPC932
002aaa497
SPICLK
MISO
MOSI
P2.3
P2.2
P2.5
P2.4
SS
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