W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 68

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

5.1.6 Bank0.Reg5 - UART Line Status Register (USR)
Power on default <7:0> = 0000,0000 binary
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG)
Power on default <7:0> = 0000,0000 binary
7-3
7-6
Bit
Bit
2
1
0
Reserved
RX_TO
OV_ERR
RDR
SMPSEL<1:0>
Name
Name
Read/Write
-
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
-
Set to 1 when receiver FIFO or frame status FIFO occurs
time-out. Read this bit will be cleared.
Received FIFO overrun. Read to clear.
This bit is set to a logical 1 to indicate received data are
ready to be read by the CPU in the RBR or FIFO. After no
data are left in the RBR or FIFO, the bit will be reset to a
logical 0.
Sampling Mode Select. Select internal decoder
methodology from the internal filter. Selected decoder
mode will determine the receive data format. The sampling
mode is shown as bellow:
SMPSEL<1:0> = 00 T-Period Sample Mode.
SMPSEL<1:0> = 01 Over-Sampling Mode.
SMPSEL<1:0> = 10 Over-Sampling with re-sync.
SMPSEL<1:0> = 11 FIFO Test Mode.
The T-period code format is defined as follows.
The Bit value is set to 0, then the high pulse will be
received. The Bit value is set to 1, then no energy will be
received. The opposite results will be generated when the
bit RXINV (Bank0.Reg6.Bit0) is set to 1.
B7 B6 B5 B4
- 59 -
Bit value
(Number of bits) - 1
Description
Description
B3
Publication Release Date: Feb. 2002
B2 B1 B0
W83697HF/F
Revision 0.70