W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 135

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

9.7.53 FAN2 Duty Cycle Select Register-- Index 03h
Power on default [7:0] = 1111,1111 b
9.7.54 FAN Configuration Register-- Index 04h
Power on default [7:0] = 0000,0000 b
7-0
7-2
5-4
3-2
Bit
Bit
1
0
F2_DC[7:0]
Reserved
FAN2_MODE
FAN1_MODE
FAN2_OB
FAN1_OB
Name
Name
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FanPWM2 Duty Cycle. This 8-bit register determines
the number of input clock cycles, out of 256-cycle period,
during which the PWM output is high. During smart fan 2
control mode, read this register will return smart fan duty
cycle.
00h: PWM output is always logical Low.
FFh: PWM output is always logical High.
XXh: PWM output logical High percentage is
XX/256*100% during one cycle.
Reserved
FAN 2 PWM Control Mode.
00 - Manual PWM Control Mode. (Default)
01 - Thermal Cruise mode.
10 - Fan Speed Cruise Mode.
11 - Reserved.
FAN 1 PWM Control Mode.
00 - Manual PWM Control Mode. (Default)
01 - Thermal Cruise mode.
10 - Fan Speed Cruise Mode.
11 - Reserved.
Enable Fan 2 as Output Buffer. Set to 0, FANPWM2
can drive logical high or logical low. Set to 1, FANPWM2
is open-drain
Enable Fan 1 as Output Buffer. Set to 0, FANP WM1
can drive logical high or logical low. Set to 1, FANPWM1
is open-drain
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Publication Release Date: Feb. 2002
Description
Description
W83697HF/F
Revision 0.70