tmp89ch42 TOSHIBA Semiconductor CORPORATION, tmp89ch42 Datasheet - Page 53

• Manufacturer Part Number: tmp89ch42
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RB000
2.4.3
Internal factor reset detection status register
(0x0FCC)
IRSTSR
Note 1: Internal reset factor flag (IRSTSR<TRMDS, TRMRF, LVD2RF, LVD1RF, SYSRF, WDTRF>) is initialized only by a power-
Note 2: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other
Note 3: If SYSCR4 is set to 0x71 after IRSTSR<FCLR> is set to "1", internal factor reset flag is cleared to "0" and IRSTSR<FCLR>
Note 4: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
Note 5: Bit 7, 6 of IRSTSR is read as "0".
clock generator.
warm-up operation that follows reset release.
exclusive use memory for adjustment of the ladder resistor that generates the comparison voltage for the power-
on reset and the voltage detection circuits.
from the reset vector address stored in addresses 0xFFFE to 0xFFFF.
circuit is reset.
the initialization of some special function registers and the initialization of the voltage detection circuits.
Functions
The power-on reset, external reset input and internal factor reset signals are input to the warm-up circuit of the
During reset, the warm-up counter circuit is reset, and the CPU and the peripheral circuits are reset.
After reset is released, the warm-up counter starts counting the high frequency clock (fc), and executes the
During the warm-up operation that follows reset release, the trimming data is loaded from the non-volatile
When the warm-up operation that follows reset release is finished, the CPU starts execution of the program
When a reset signal is input during the warm-up operation that follows reset release, the warm-up counter
The reset operation is common to the power-on reset, external reset input and internal factor resets, except for
When a reset is applied, the peripheral circuits become the states as shown in Table 2-5.
LVD2RF
LVD1RF
TRMDS
TRMRF
WDTRF
Read/Write
SYSRF
Bit Symbol
After reset
on reset, an external reset input or IRSTSR <FCLR>. It is not initialized by an internal factor reset.
effects.
is automatically cleared to "0".
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
FCLR
Flag initialization control
Trimming data status
Trimming data reset detection flag
Voltage detection reset 2 detection
flag
Voltage detection reset 1 detection
flag
System clock reset detection flag
Watchdog timer reset detection flag
FCLR
W
7
0
R
6
0
-
TRMDS
R
5
0
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0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
-
Clears the internal factor reset flag to "0".
-
Detect state of abnormal trimming data
-
Detects the trimming data reset.
-
Detects the voltage detection 2 reset.
-
Detects the voltage detection 1 reset.
-
Detects the system clock reset.
-
Detects the watchdog timer reset.
TRMRF
R
4
0
LVD2RF
R
3
0
LVD1RF
R
2
0
SYSRF
R
1
0
TMP89CH42
WDTRF
R
0
0