tmp89ch42 TOSHIBA Semiconductor CORPORATION, tmp89ch42 Datasheet - Page 232

• Manufacturer Part Number: tmp89ch42
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

16.2
Control
RA001
UART0 control register 1
UART0CR1
(0x001A)
Note 1: fcgck, Gear clock; fs, Low-frequency clock
Note 2: If the TXE or RXE bit is set to "0" during the transmission or receiving of data, the operation is not disabled until the data
Note 3: EVEN, PE and BRG settings are common to transmission and receiving.
Note 4: Set RXE and TXE to "0" before changing BRG.
Note 5: When BRG is set to the TCA0 output, the RT clock becomes asynchronous and the start bit of the transmitted/received
Note 6: To prevent STOPBT, EVEN, PE, IRDASEL and BRG from being changed accidentally during the UART communication,
Note 7: When the STOP, IDLE0 or SLEEP0 mode is activated, TXE and RXE are cleared to "0" and the UART stops. Other bits
IRDASEL
STOPBT
Read/Write
transfer is completed. At this time, the data stored in the transmit data buffer is discarded.
data may get shorter by a maximum of (UART0DR+1)/(Transfer base clock frequency)[s].
If the pin is not used for the TCA0 output, control the TCA0 output by using the port function control register.
the register cannot be rewritten during the UART operation. For details, refer to "16.4 Protection to Prevent UART0CR1
and UART0CR2 Registers from Being Changed ".
keep their values.
Bit Symbol
EVEN
After reset
BRG
TXE
RXE
PE
Transmit operation
Receive operation
Transmit stop bit length
Parity selection
Parity addition
TXD pin output selection
Transfer base clock selection
TXE
R/W
7
0
RXE
R/W
6
0
STOPBT
R/W
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5
0
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
Disable
Enable
Disable
Enable
1 bit
2 bits
Odd-numbered parity
Even-numbered parity
No parity
Parity added
UART output
IrDA output
When SYSCR2<SYSCK> is "0"
EVEN
R/W
4
0
fcgck
R/W
PE
3
0
TCA0 output
IRDASEL
R/W
2
0
When SYSCR2<SYSCK> is "1"
BRG
R/W
1
0
fs
TMP89CH42
R
0
0
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