tmp89fm46a TOSHIBA Semiconductor CORPORATION, tmp89fm46a Datasheet - Page 63

• Manufacturer Part Number: tmp89fm46a
• Description: Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3
System clock controller
RA000
Quarter of the low-frequency clock
Figure 2-15 Switching the Main System Clock (fm) (Switching from fs/4 to fcgck)
VINTWUC:
SYSCR2<SYSCK>
Gear clock (fcgck)
Main system clock
Example : Switching from the SLOW1 mode to the NORMAL1 mode after the stability of the external high-frequency clock
(2)
Confirm at the warm-up counter that the oscillation of the reference clock for the high-frequency clock
has stabilized, and then clear SYSCR2<SYSCK> to "0".
main system clock (fm) is switched to fcgck.
off the external low-frequency clock oscillator.
voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up operation,
the NORMAL1 mode becomes active.
Note 1: Be sure to follow this procedure to switch the operation from the SLOW1 mode to the NORMAL1
Note 2: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clearing
Note 3: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock
Note 4: SYSCR1<OSCSEL> should be set while SYSCR2<SYSCK> is "0" (during the NORMAL1 or
Note 5: When P0FC0 is "0", setting SYSCR2<XEN> to "1" causes a system clock reset.
Note 6: When SYSCR2<XEN> is set at "1", writing "1" to SYSCR2<XEN> does not cause the warm-up
Set SYSCR2<OSCEN> or SYSCR2<XEN> to "1" to enable the high-frequency reference clock (fh).
When a maximum of 8/fs + 2.5/fcgck [s] has elapsed since SYSCR2<SYSCK> is cleared to "0", the
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XTEN> to "0" to turn
The SLOW mode is also released by a reset by the RESET pin, a power-on reset and a reset by the
(fs/4)
Switching from the SLOW1 mode to the NORMAL1 mode
DW
; #### Initialize routine ####
SET
¦
¦
LD
LD
oscillation circuit is confirmed at the warm-up counter (fc = 10 MHz, warm-up time = 4.0 ms)
mode.
SYSCR2<XTEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization, fm is
stopped for a period of 2.5/fcgck [s] or shorter.
NORMAL 2 mode). Writing to SYSCR1<OSCSEL> while SYSCR2<SYSCK> is "1" (during the
SLOW1 or SLOW2 mode) has no effect.
counter to start counting the source clock.
PINTWUC
(P0FC).2
(WUCCR), 0x09
(WUCDR), 0x9D
When the rising edge of fs/4 is
detected twice after SYSCR2<SYSCK>
is changed from 1 to 0, f is stopped
for synchronization.
Page 44
;INTWUC vector table
;P0FC2 = 1 (Uses P02/03 as oscillators)
;WUCCR<WUCDIV> = 10 (Divided by 2)
;WUCCR<WUCSEL> = 0 (Selects fc as the source clock)
;Sets the warm-up time
;(Determine the time depending on the frequency and the oscillator
2.5/fcgck(max.)
When the rising edge of fcgck is detected
twice after fm is stopped, fm is switched to fcgck.
TMP89FM46A