tmp89fm46a TOSHIBA Semiconductor CORPORATION, tmp89fm46a Datasheet - Page 46

• Manufacturer Part Number: tmp89fm46a
• Description: Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
2.3.4.2
Note 1: When the operation is switched to the STOP mode during the warm-up for the oscillation enabled by the software, the
Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains
oscillation becomes stable, at a mode change from NORMAL1 to NORMAL2 or from SLOW1 to SLOW2.
SYSCR2<XTEN> to "1" allows the stopped oscillation circuit to start oscillation and the 14-stage counter to
start counting the selected input clock.
(2)
warm-up counter holds the value at the time, and restarts counting after the STOP mode is released. In this case, the
warm-up time at the release of the STOP mode becomes insufficient. Don't switch the operation to the STOP mode during
the warm-up for the oscillation enabled by the software.
errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for
the oscillation start property of the oscillator.
The warm-up counter serves to secure the time after the oscillation is enabled by the software before the
Select the input clock to the frequency division circuit at WUCCR<WUCSEL>.
Select the input clock to the 14-stage counter at WUCCR<WUCDIV>.
After the warm-up time is set at WUCDR, setting SYSCR2<OSCEN>, SYSCR2<XEN> or
Warm-up counter operation when the oscillation is enabled by the software
Clock that generated the main
system clock when the STOP
the oscillation becomes stable at the release of the STOP mode.
as the input clock for the frequency division circuit, regardless of WUCCR<WUCSEL>.
at WUCCR<WUCDIV> and set the warm-up time at WUCDR.
frequency division circuit.
the operation is restarted by an instruction that follows the STOP mode activation instruction.
mode was activated
WUCDR is initialized to 0x66 after reset release, which makes the warm-up time 0x66 × 2
The warm-up counter serves to secure the time after the oscillation is enabled by the hardware before
The clock that was used to generate the main system clock when STOP mode was activated is selected
Before the STOP mode is activated, select the division rate of the input clock to the warm-up counter
When the STOP mode is released, the 14-stage counter starts counting the input clock selected in the
When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and
Note:The clock output from the oscillation circuit is used as the input clock to the warm-up counter.
When the STOP mode is released
fosc
The warm-up time contains errors because the oscillation frequency is unstable until the oscil-
lation circuit becomes stable.
fc
fs
<WUCSEL>
Don’t Care
Don’t Care
Don't Care
WUCCR
<WUCDIV>
Page 27
WUCCR
00
01
10
11
00
01
10
11
00
01
10
11
Counter input
fosc / 2
fosc / 2
fosc / 2
fc / 2
fc / 2
fs / 2
fs / 2
clock
fc / 2
fs / 2
fosc
fc
fs
2
3
2
3
2
3
2
2
2
2
6
7
8
9
2
2
2
2
2
2
2
2
/ fosc to 255 × 2
/ fosc to 255 × 2
/ fosc to 255 × 2
/ fosc to 255 × 2
6
7
8
9
6
7
8
9
/ fc to 255 × 2
/ fc to 255 × 2
/ fc to 255 × 2
/ fc to 255 × 2
/ fs to 255 × 2
/ fs to 255 × 2
/ fs to 255 × 2
/ fs to 255 × 2
Warm-up time
6
7
8
9
6
6
8
9
6
7
8
9
/ fosc
/ fosc
/ fosc
/ fosc
/ fc
/ fc
/ fc
/ fc
/ fs
/ fs
/ fs
/ fs
TMP89FM46A
9
/fosc[s].