tmp89fm46a TOSHIBA Semiconductor CORPORATION, tmp89fm46a Datasheet - Page 16

• Manufacturer Part Number: tmp89fm46a
• Description: Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

19. Key-on Wakeup (KWU)
20. 10-bit AD Converter (ADC)
21. Flash Memory
18.5 Data Transfer of I2C Bus.....................................................................................................288
18.6 AC Specifications................................................................................................................295
19.1 Configuration.......................................................................................................................297
19.2 Control.................................................................................................................................298
19.3 Functions..............................................................................................................................299
20.1 Configuration.......................................................................................................................301
20.2 Control.................................................................................................................................302
20.3
20.4
20.5 Starting STOP/IDLE0/SLOW Modes.................................................................................308
20.6 Analog Input Voltage and AD Conversion Result..............................................................309
20.7 Precautions about the AD Converter...................................................................................310
21.1 Flash Memory Control.........................................................................................................312
21.2 Functions..............................................................................................................................315
21.3 Command Sequence............................................................................................................322
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
18.4.13
18.4.14
18.4.15
18.5.1
18.5.2
18.5.3
18.5.4
18.5.5
20.3.1
20.3.2
20.3.3
20.7.1
20.7.2
20.7.3
21.2.1
21.2.2
21.2.3
21.2.4
21.2.5
21.2.6
21.3.1
21.3.2
21.3.3
21.3.4
18.5.3.1
18.5.3.2
Functions.............................................................................................................................306
Register Setting...................................................................................................................308
Start/stop condition generation......................................................................................................................................282
Interrupt service request and release..............................................................................................................................283
Setting of serial bus interface mode...............................................................................................................................284
Device initialization.......................................................................................................................................................288
Start condition and slave address generation.................................................................................................................288
1-word data transfer.......................................................................................................................................................289
Stop condition generation..............................................................................................................................................292
Restart............................................................................................................................................................................293
Single mode...................................................................................................................................................................306
Repeat mode..................................................................................................................................................................306
AD operation disable and forced stop of AD operation................................................................................................307
Analog input pin voltage range......................................................................................................................................310
Analog input pins used as input/output ports.................................................................................................................310
Noise countermeasure....................................................................................................................................................310
Flash memory command sequence execution and toggle control (FLSCR1 <FLSMD>).............................................315
Flash memory area switching (FLSCR1<FAREA>).....................................................................................................316
RAM area switching (SYSCR3<RAREA>)..................................................................................................................318
BOOTROM area switching (FLSCR1<BAREA>).......................................................................................................318
Flash memory standby control (FLSSTB<FSTB>).......................................................................................................320
Port input control register (SPCR<PIN0, PIN1>).........................................................................................................321
Byte program.................................................................................................................................................................322
Sector erase (4-kbyte partial erase)................................................................................................................................323
Chip erase (all erase)......................................................................................................................................................323
Product ID entry.............................................................................................................................................................324
Software reset..............................................................................................................................................................284
Arbitration lost detection monitor................................................................................................................................284
Slave address match detection monitor.......................................................................................................................286
GENERAL CALL detection monitor..........................................................................................................................286
Last received bit monitor.............................................................................................................................................287
Slave address and address recognition mode specification.........................................................................................287
When SBI0SR2<MST> is "1" (Master mode)
When SBI0SR2<MST> is "0" (Slave mode)
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