dm9332 Davicom Semiconductor, Inc., dm9332 Datasheet - Page 15

• Manufacturer Part Number: dm9332
• Description: 10/100mbps Ethernet Fiber/twisted Pair Single Chip Media Converter
• Manufacturer: Davicom Semiconductor, Inc.

6. Control and Status Register Set
The DM9332 implements several control and status
registers, which can be accessed by the serial management
interface. These CSRs are byte aligned. All CSRs are set to
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
<Reset Value>:
P = power on reset default value
H = hardware reset, by Reg. 52H bit 6, default value
Preliminary datasheet
DM9332-15-DS-P01
August 26, 2009
Register
VLAN_TAGH
VLAN_TAGL
P_UNKNWN
P_UNICAST
SWITCHCR
SWITCHSR
VLAN_MAP
P_MIB_IDX
1
0
X
TOS_MAP
P_BCAST
P_INDEX
MIB_DAT
MIB_DAT
MIB_DAT
MIB_DAT
P_MULTI
VLANCR
P_STUS
P_RATE
P_CTRL
EPDRH
EPDRL
DSP1,2
PVLAN
P2FRV
P_BW
P_PRI
EPCR
EPAR
VID
Bit set to logic one
Bit set to logic zero
No default value
Description
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Vendor ID
Port 2 driving capability Register
SWITCH Control Register
VLAN Control Register
SWITCH Status Register
DSP Control Register I,II
Per Port Control/Status Index Register
Per Port Control Data Register
Per Port Status Data Register
Per Port Ingress and Egress Rate Control Register
Per Port Bandwidth Control Register
Per Port Block Unicast ports Control Register
Per Port Block Multicast ports Control Register
Per Port Block Broadcast ports Control Register
Per Port Block Unknown ports Control Register
Per Port Priority Queue Control Register
Per Port VLAN Tag Low Byte Register
Per Port VLAN Tag High Byte Register
Per Port MIB counter Index Register
MIB counter Data Register bit 0~7
MIB counter Data Register bit 8~15
MIB counter Data Register bit 16~23
MIB counter Data Register bit 24~31
Port-based VLAN mapping table registers
TOS Priority Map Register
VLAN priority Map Register
10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
their default values by hardware or software reset unless
specified
E = default value from EEPROM setting
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits should be written with 0.
Reserved bits are undefined on read access.
Offset
0BH
0CH
0DH
0EH
28H-29H
3AH
52H
53H
54H
58H~59H
60H
61H
62H
66H
67H
68H
69H
6AH
6BH
6DH
6EH
6FH
80H
81H
82H
83H
84H
B0-BFH
C0-CFH
D0-D1H
Default value
after reset
00H
40H
XXH
XXH
0A46H
21H
00H
00H
00H
0000H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
01H
00H
00H
00H
00H
00H
00H
0FH
00H~FFH
50H,FAH
DM9332
15