dm9332 Davicom Semiconductor, Inc., dm9332 Datasheet
dm9332
Related parts for dm9332
dm9332 Summary of contents
Page 1
... DAVICOM Semiconductor, Inc. 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DATA SHEET DM9332 Preliminary Version: DM9332-DS-P01 August 26, 2009 ...
Page 2
... LED Pins ......................................................................................................................................................... 12 5.4 Clock Interface............................................................................................................................................... 13 5.5 Network Interface .......................................................................................................................................... 13 5.6 Miscellaneous Pins ....................................................................................................................................... 13 5.7 Power Pins ..................................................................................................................................................... 13 5.8 Strap pins table.............................................................................................................................................. 14 6. CONTROL AND STATUS REGISTER SET................................................................... 15 6.1 EEPROM & PHY Control Register (0BH) ..................................................................................................... 16 2 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter CONTENT DM9332 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 3
... Per Port Block Unknown ports Control Register (6BH) .......................................................................... 22 6.19 Per Port Priority Queue Control Register (6DH)....................................................................................... 22 6.20 Per Port VLAN Tag Low Byte Register (6EH) ........................................................................................... 22 6.21 Per Port VLAN Tag High Byte Register (6FH)........................................................................................... 23 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 3 ...
Page 4
... Configuration/Status (10BTCSR) – 12H.................................................................................. 40 8.11 Power down Control Register (PWDOR) – 13H ........................................................................................ 40 8.12 (Specified config) Register – 14H .............................................................................................................. 41 8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H ..................................................... 42 4 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 5
... Tag/Untag ........................................................................................................................................... 46 9.2.14 Priority Support ...................................................................................................................................... 47 9.2.14.1 Port-Based Priority .............................................................................................................................. 47 9.2.14.2 802.1p-Based Priority.......................................................................................................................... 47 9.2.14.3 DiffServ-Based Priority........................................................................................................................ 47 9.3 MII Interface.................................................................................................................................................... 48 9.3.1 MII data interface ..................................................................................................................................... 48 9.3.2 MII Serial Management ............................................................................................................................ 48 9.3.3 Serial Management Interface ................................................................................................................... 49 9.3.4 Management Interface - Read Frame Structure ...................................................................................... 49 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 5 ...
Page 6
... Decoder....................................................................................................................................... 53 9.4.3 10Base-T Operation................................................................................................................................. 53 9.4.4 Collision Detection ................................................................................................................................... 53 9.4.5 Carrier Sense ........................................................................................................................................... 53 9.4.6 Auto-Negotiation ...................................................................................................................................... 53 9.5 HP Auto-MDIX Functional Descriptions ...................................................................................................... 53 10. DC AND AC ELECTRICAL CHARACTERISTICS ..................................................... 55 10.1 Absolute Maximum Ratings ....................................................................................................................... 55 10.2 Operating Conditions.................................................................................................................................. 55 10.3 DC Electrical Characteristics ..................................................................................................................... 56 6 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 7
... Power On Reset Timing ......................................................................................................................... 56 10.4.2 Port 2 MII Interface Transmit Timing...................................................................................................... 57 10.4.3 Port 2 MII Interface Receive Timing....................................................................................................... 57 10.4.4 MII Management or host SMI Interface Timing...................................................................................... 58 10.4.5 EEPROM timing ..................................................................................................................................... 59 11. PACKAGE INFORMATION........................................................................................ 60 12. ORDERING INFORMATION ...................................................................................... 61 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 7 ...
Page 8
... General Description The DM9332 is a fully integrated and cost-effective 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter with MII/RMII Interface. This new product provides basic Layer-2 switch functions and advance IEEE 802.1Q VLAN, priority queuing scheme. Besides the DM9332 Fiber converter is complies with IEEE802 ...
Page 9
... EEPROM interface for power up configurations Support MIB-II counters Compatible with 3.3V and 5.0V tolerant I/O DSP PHY with HP Auto-MDIX, DSP architecture PHY Transceiver. 64-pin LQFP, 0.18 um process, support Lead-Free and Halogen–Free Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 9 ...
Page 10
... Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 DM9332 TEST1 32 GND 31 30 PWRST# 29 EECS EECK 28 27 EEDIO 26 VCC3 RXD2_0 25 RXD2_1 24 GND 23 22 RXD2_2 RXD2_3 21 RXDV2 20 19 RXC2 18 RXER COL2 17 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 11
... TXC2 O Reserved TXER2 O Port 2 MII Transmit Error CRS2 I RMII CRS_DV COL2 I Reserved, tie to ground in application. RXER2 I Reserved, tie to ground in application. RXC2 I 50MHz reference clock. RXDV2 I Reserved, tie to ground in application. RXD2_3~2 I Reserved, tie to ground in application. RXD2_1~0 I RMII Receive Data. DM9332 Description Description 11 ...
Page 12
... It is the combined LED of link and carrier sense signal of the internal PHY0 SPD0_LED O Port 0 Speed LED Its low output indicates that the internal PHY0 is operated in 100M/ floating for the 10M mode of the internal PHY0 DM9332 Description Description Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 13
... Serial data management interface in / out TEST1 I,PD Tie to VCC3 in application TEST2 I,PD Tie to GND in application TEST3 I,PD Tie to VCC3 in application Pin Name I/O VCC3 P Digital 3.3V VCCI P Internal 1.8V core power GND P Digital GND AVDD3 P Analog 3.3V power AVDDI P Analog 1.8V power AGND P Analog GND DM9332 Description Description Description Description 13 ...
Page 14
... SMI device address 0 10 TXE2 0: Port 2 normal mode 1: Port 2 force mode 14 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter TXD2_3 TXD2_2 Mode 0 0 MII mode 0 1 Reverse MII mode 1 0 RMII mode 1 1 Reserved (DO NOT USE) DM9332 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 15
... Control and Status Register Set The DM9332 implements several control and status registers, which can be accessed by the serial management interface. These CSRs are byte aligned. All CSRs are set to Register Description EPCR EEPROM & PHY Control Register EPAR EEPROM & PHY Address Register EPDRL EEPROM & ...
Page 16
... This data is made to write/read high byte of word address defined in Reg EEPROM or PHY Vendor ID High Byte (29H) Vendor ID Low Byte (28H) Reserved Port 2 TXD/TXE Driving/Sinking Capability 00: 2mA 01: 4mA (default) 10: 6mA 11: 8mA reserved DM9332 Description Description Description Description Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 17
... VLAN tag defined in Reg. 6EH and 6FH. Replace priority field in the tag with value define in Reg 6FH bit 7~5. VLAN mode enable 1: 802.1Q base VLAN mode enable 0: port-base VLAN only Address Table Memory Test BIST Status Fail Reserved DM9332 Description Description Description 17 ...
Page 18
... Link Partner Flow Control Enable Status BIST status 1: SRAM BIST fail 0: SRAM BIST pass Reserved PHY Speed Status 0: 10Mbps, 1:100Mbps PHY Duplex Status 0: half-duplex, 1:full-duplex PHY Link Status 0: link fail, 1: link OK DM9332 Description Description Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 19
... The received broadcast or multicast packets are not forward to sniffer port. Reserved Packet Transmit Disabled All packets can not be forward to this port. Packet receive Disabled All received packets are discarded. Address Learning Disabled The Source Address (SA) field of packet is not learned to address table. DM9332 Description 19 ...
Page 20
... DM9332 Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 21
... Reserved Ports of Unicast Packet Be Blocked The received unicast packets are not forward to the assigned ports. Note that the assigned port definition: bit 0 for port 0, bit 1 for port 1, DM9332 Description Description 21 ...
Page 22
... The priority information from ToS field of IP packet is ignored. 802.1 p Priority Classification Disable The priority information from VLAN tag field is ignored. Port Base priority The priority queue number in port base. 00= queue 0, 01=queue 1, 10=queue 2, 11=queue 3 VID[7:0] DM9332 Description Description Description Description Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 23
... MIB data is ready. Reserved MIB counter index 0~9, each counter is 32-bit in Register 81h~84h. Write the MIB counter index to this register before read them. Counter’s data bit 7~0 Counter’s data bit 15~8 Counter’s data bit 23~16 Counter’s data bit 31~24 DM9332 Description Description Description 23 ...
Page 24
... If bit 53H.7 =1 :TOS[7:2]=0BH If bit 53H.7 =1 :TOS[7:2]=0AH If bit 53H.7 =1 :TOS[7:2]=09H If bit 53H.7 =1 :TOS[7:2]=08H If bit 53H.7 =1 :TOS[7:2]=0FH If bit 53H.7 =1 :TOS[7:2]=0EH If bit 53H.7 =1 :TOS[7:2]=0DH If bit 53H.7 =1 :TOS[7:2]=0CH DM9332 Description Description Description Description Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 25
... If bit 53H.7 =1 :TOS[7:2]=1CH If bit 53H.7 =1 :TOS[7:2]=23H If bit 53H.7 =1 :TOS[7:2]=22H If bit 53H.7 =1 :TOS[7:2]=21H If bit 53H.7 =1 :TOS[7:2]=20H If bit 53H.7 =1 :TOS[7:2]=27H If bit 53H.7 =1 :TOS[7:2]=26H If bit 53H.7 =1 :TOS[7:2]=25H If bit 53H.7 =1 :TOS[7:2]=24H DM9332 Description Description Description Description Description Description 25 ...
Page 26
... If bit 53H.7 =1 :TOS[7:2]=3AH If bit 53H.7 =1 :TOS[7:2]=39H If bit 53H.7 =1 :TOS[7:2]=38H If bit 53H.7 =1 :TOS[7:2]=3FH If bit 53H.7 =1 :TOS[7:2]=3EH If bit 53H.7 =1 :TOS[7:2]=3DH If bit 53H.7 =1 :TOS[7:2]=3CH DM9332 Description Description Description Description Description Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 27
... VLAN priority tag value = 03H VLAN priority tag value = 02H VLAN priority tag value = 01H VLAN priority tag value = 00H VLAN priority tag value = 07H VLAN priority tag value = 06H VLAN priority tag value = 05H VLAN priority tag value = 04H DM9332 Description Description 27 ...
Page 28
... This word bit 7~0 will be loaded to port 1 Reg. 6EH bit 7~0 This word bit 15~8 will be loaded to port 1 Reg. 6FH bit 7~0 When word 16 bit 5:4 is “01”, after power on reset: This word bit 7~0 will be loaded to port 2 Reg. 6EH bit 7~0 DM9332 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 29
... When word 16 bit 11:10 is “01”, after power on reset: This word bit 7~0 will be loaded to Reg. CAH bit 7~0 This word bit 15~8 will be loaded to Reg. CBH bit 7~0 When word 16 bit 11:10 is “01”, after power on reset: This word bit 7~0 will be loaded to Reg. CCH bit 7~0 DM9332 29 ...
Page 30
... Ethernet Fiber/Twisted Pair Single Chip Media Converter This word bit 15~8 will be loaded to Reg. CDH bit 7~0 When word 16 bit 11:10 is “01”, after power on reset: This word bit 7~0 will be loaded to Reg. CEH bit 7~0 This word bit 15~8 will be loaded to Reg. CFH bit 7~0 DM9332 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 31
... St. Mch Supr. PHY ADDR [4:0] Auto-N. Monitor Bit [3:0] Reserved PDchip PDcrm PDaeq PDdrv PDecli AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve _dlpbk Value wn Disconnect_counter Reversed DM9332 1 0 Jabber Extd Detect Cap Version No. 0000 New Pg LP AutoN Rcv Cap. Sleep Reserved mode ...
Page 32
... When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9332. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit ...
Page 33
... DM9332 is not able to perform in 100BASE-T4 mode 1,RO/P 100BASE-TX Full Duplex Capable 1 = DM9332 is able to perform 100BASE-TX in full duplex mode 0 = DM9332 is not able to perform 100BASE-TX in full duplex mode 1,RO/P 100BASE-TX Half Duplex Capable 1 = DM9332 is able to perform 100BASE-TX in half duplex mode 0 = DM9332 is not able to perform 100BASE-TX in half duplex ...
Page 34
... PHY ID Identifier Register #1 (PHYID1) – 02H The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9332. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. ...
Page 35
... Auto-negotiation Advertisement Register (ANAR) – 04H This register contains the advertised abilities of this DM9332 device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name ACK 13 RF 12-11 Reserved 10 FCS TX_FDX 7 TX_HDX 6 10_FDX 5 10_HDX 4-0 Selector <00001>, RW Protocol Selection Bits ...
Page 36
... Link partner, next page available 0, RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9332's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit 0, RO Remote Fault 1 = Remote fault indicated by link partner ...
Page 37
... Local Device Next Page Able NP_ABLE = 1: DM9332, next page available NP_ABLE = 0: DM9332, no next page DM9332 does not support this function, so this bit is always New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management ...
Page 38
... When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset 0, RW Reserved Force application. DM9332 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 39
... Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal link ready Parallel detects signal link ready fail Auto-negotiation completed successfully DM9332 Description 39 ...
Page 40
... Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9332 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) Squelch Enable 1 = Normal squelch ...
Page 41
... When Mdix_down = 1, MDIX_CNTL value depend on the register value. 0,RW MDIX Down Manual force MDI/MDIX. 0: Enable HP Auto-MDIX 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on Reg.14H.bit5 0,RW Vendor monitor select 1 0,RW Vendor monitor select 0 0,RW Reserved Force application. 0,RW Power down control value Decision the value of each field Reg.13H. 1: power down 0: normal DM9332 Description 41 ...
Page 42
... Transmit amplitude reduce function 0.RW Transmit Power Saving Control Disabled 1: when cable is unconnected with link partner, the driving current of transmit is reduced for power saving. 0: disable transmit driving power saving function 0,RO RESERVED DM9332 Description Description Description Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 43
... Register Address Write pin (TXD2_0 & TXD2_1). The <Register Address> field of the frame is mapped to address of control and status register set of DM9332. The read/writ data is valid on low byte (D7~D0) of <Data> field, the high byte (D15~D8) of data is reserved. 2. DM9332 supports MII SMI auto-polling for configuring speed, duplex mode, and 802 ...
Page 44
... The DM9332 supports half-duplex backpressure. The inducement is the same as full duplex mode. When flow control is required, the DM9332 sends jam pattern and results in a collision. The flow control ability can be set in bit 4 of register 61h. ...
Page 45
... If a packet is received form port 0 and predestined to port 1 after forwarding decision, the DM9332 will forward it to port 1 and port 2 in the end. (3).Transmit monitor All packets transmitted on the “transmit monitor port” ...
Page 46
... The DM9332 supports port-based VLAN as default groups. Each port has a default VID called PVID (Port VID, see register 6Fh). The DM9332 used LSB 4-bytes of PVID as index and mapped to register B0h~BFh, to define the VLAN groups. For instance, we intend to partition DM9332’s ports into three groups ...
Page 47
... The DM9332 will insert the PVID tag when an untagged packet enters the port, and recalculate CRC before delivering it. (4). Receive tagged packet and forward to Tag port. Received packet will forward to destination port without modification. 9.2.14 Priority Support The DM9332 supports Quality of Service (QoS) mechanism for multimedia communication such as VoIP and video conferencing ...
Page 48
... DM9332 port 2 MAC reconciliation sub layer. • RXC2 (receive clock) from external device to the DM9332 port 2 MAC reconciliation sub layer is a continuous clock that provides the timing reference for the transfer of the RXDV2, RXD2, and RXER2 signals. ...
Page 49
... Ethernet Fiber/Twisted Pair Single Chip Media Converter Code PHY Address Register Address Write Code PHY Address Register Address Write DM9332 // R0 0 D15 D14 Turn Around Data Read D15 D14 D1 D0 Turn Around Data // Idle ...
Page 50
... The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately transformer’s primary winding, resulting in a minimal current MLT-3 signal. DM9332 drives either side of the Preliminary datasheet DM9332-15-DS-P01 transmit August 26, 2009 ...
Page 51
... Invalid undefined Invalid undefined Invalid undefined Invalid undefined Invalid undefined Invalid undefined Invalid undefined Invalid undefined Invalid undefined Table 1 DM9332 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 ...
Page 52
... Ethernet Fiber/Twisted Pair Single Chip Media Converter 9.4.2.3 MLT-3 to NRZI Decoder The DM9332 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. 9.4.2.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125 MHz reference clock ...
Page 53
... The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer. 9.4.3 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9332 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial bit stream, then the Manchester encoded. ...
Page 54
... from DM9332 from DM9332 * MDI: __________ * MDIX 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DM9332 RX+/- to RJ45 TX+/- to RJ45 Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 55
... DM9332 Conditions Lead-free Device Conditions - - - - 1.8VD only 1.8VA only 3.3VD only 3.3VA only 1.8VD only 1.8VA only 3.3VD only 3.3VA only 1.8VD only 1.8VA only 3.3VD only 3.3VA only 1.8VD only 1.8VA only 3.3VD only 3 ...
Page 56
... Unit Conditions 0.8 V Vcond1 - V Vcond1 - uA VIN = 0.0V, Vcond1 1 uA VIN = 3.3V, Vcond1 0.4 V IOL = 4mA - V IOH = -4mA - V 100 Ω Termination Across 2.1 V Peak to Peak 5.6 V Peak to Peak │21│ mA Absolute Value │56│ mA Absolute Value Max. Unit Conditions - - Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 57
... Port 2 MII Interface Receive Timing RXC2 RXER2,RXDV2 RXD2_3~0 Symbol T1 RXER2, RXDV2,RXD2_3~0 Setup Time T2 RXER2, RXDV2,RXD2_3~0 Hold Time Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter T1 Parameter T1 Parameter DM9332 T2 Min. Typ. Max Min. Typ. Max Unit ns ns Unit ...
Page 58
... MDIO (drived by DM9332) or SMI_DIO MDIO (drived by exetrnal MII) or SMI_DIO Symbol T1 MDC or SMI_CK Frequency T2 MDIO or SMI_DIO by DM9332 Setup Time T3 MDIO or SMI_DIO by DM9332 Hold Time T4 MDIO or SMI_DIO by External MII Setup Time T5 MDIO or SMI_DIO by External MII Hold Time 58 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter ...
Page 59
... T5 EEDIO Hold Time in output state T6 EEDIO Setup Time in input state T7 EEDIO Hold Time in input state Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Parameter DM9332 Min. Typ. Max. 480 2080 0.38 460 2100 ...
Page 60
... BSC 0.394 BSC 0.472 BSC 0.394 BSC 0.020 BSC 0.018 0.024 0.030 0.039 REF 0.003 - - 0.003 - 0.008 0.008 - - 3 TYP o 12 TYP Preliminary datasheet DM9332-15-DS-P01 August 26, 2009 ...
Page 61
... Ethernet networking standards. DM9332 Semiconductor Inc. develops Our currently and 61 ...