ncp5424adr2 ON Semiconductor, ncp5424adr2 Datasheet - Page 8

• Manufacturer Part Number: ncp5424adr2
• Description: Dual Synchronous Buck Controller With Input Current Sharing
• Manufacturer: ON Semiconductor

allow a short PWM pulse. This pulse will gradually increase
in width as the voltage ramp on the Compensation Capacitor
continues to rise. This process will continue until the output
voltage reaches the designed value set by the feed back
resistors and the parts 1.0−volt reference voltage. Thus the
user can determine both Soft−Start and power sequence
functions by selecting the compensation capacitors and
simply knowing that the amplifiers charge these capacitors
with 30 uA and that the threshold for starting PWM pulses
is 0.45 volts.
Normal Operation
remains approximately constant as the V
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load
conditions will result in changes in duty cycle to maintain
regulation.
Zero Current Start Up in Single Output Shared Input
Current Applications
connected as a single output is that reverse currents can
occur during zero load conditions. As the two controllers
start up and start delivering current, if there is no load a
reverse current will develop in the inductor of controller 2
that is equal and opposite the current in the controller 1
inductor. When the controller 2 starts to deliver power this
reverse current will flow backwards through the top FET
back into the supply. In the extreme this can cause the supply
to over voltage and/or shut down. Fortunately, there are
several ways to deal with this problem. One is to simply
insure the part has a minimum load. Another is illustrated in
Figure 5, where a diode and voltage divider biases the
controller 2 Compensation Capacitor above the 0.45 V
Soft−Start threshold, such that the controller starts switching
without a soft−start delay. The effect of this is to eliminate
0.45 V
8.6 V
During normal operation, the duty cycle of the gate drivers
One problem that occurs with dual controllers when
UVLO
Figure 4. Idealized Waveforms
STARTUP
t
S
NORMAL OPERATION
2
control loop
V
V
V
GATE(H)1
GATE(H)2
IN
COMP
FB
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NCP5424
8
the buildup of negative currents that arise during a long start
interval where the bottom FET of controller 2 is on. For
applications where there are two outputs, this problem can
not occur.
Gate Charge Effect on Switching Times
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading,
according to the following graphs.
Transient Response
transient response to any variations in input voltage and
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
COMP2
When using the onboard gate drivers, the gate charge has
The 150 ns reaction time of the control loop provides fast
90
80
70
60
50
40
30
20
10
0
0
Figure 6. Average Rise and Fall Times
Figure 5. Preventing Reverse Current
1
Average Fall Time
Comp
Cap
2
3
Load (nF)
(V
4
IN
0.958
− 1.15)
5
Average Rise Time
kW
6
1.2 kW
V
7
IN
8