ncp5424adr2 ON Semiconductor, ncp5424adr2 Datasheet - Page 14

• Manufacturer Part Number: ncp5424adr2
• Description: Dual Synchronous Buck Controller With Input Current Sharing
• Manufacturer: ON Semiconductor

where:
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
Selection of the Current Sharing Ratio
single output two−phase Buck Converter, the two
controllers are in a Master−Slave configuration. The Slave
controller on the right side of Figure 1 tries to follow
information provided by the Master controller, on the left.
The circuit uses inductor current sensing, in which the
parasitic resistance (LSR) of the controller’s output chokes
are used as a current sensing element. On the Slave side
(Controller Two), both Error Amplifier inputs are brought to
external pins so the reference is available. The RC network
in parallel with the output inductor on the Master side
(Controller One) generates the reference for the Slave.
Current information from the Slave is fed back to the error
amplifier’s inverting input. In this configuration, the Slave
tries to adjust its current to match the current information fed
to its reference input from the Master Controller. In Figure 1,
R1, R2 and C6 are used to generate the Slave’s reference.
R17 and C14 generate the Slave’s inverting input signal. If
50−50 current sharing is needed, then only R2 and C6 are
required to generate the reference signal. The values for both
sides should be calculated with the following equation.
where:
constant, the voltage across the capacitor will be equal to the
voltage drop across the internal resistance of the inductor. For
proper sharing, the inductors on both sides should be the same.
of the inverting signal filter are calculated using the previous
equation. Since the reference signal has to be divided down
to the proper ratio, R1 is required. Using the same
capacitance value, the following equation is used to
calculate the proper values for the reference filter.
where:
resistance of R1 and R2 should be greater or equal to the value
R17, the resistance value calculated for the inverting signal.
P
Q
f
The junction temperature of the control IC is primarily a
When the two controllers are connected together as a
L = Inductor value, both Controllers should use the
RL = Internal resistance of L, from inductor data sheet.
C6 = Select a value such that R < 15 kW.
With the RC time constant selected to equal the L/R
If a ratio other than 50−50 is needed, the R and C values
R1 = Chosen Value, 10 kW is recommended.
To ensure greater accuracy, the equivalent parallel
SW
GATE(L)
GATE(L)
= switching frequency;
same inductor.
Ratio + %slave
= lower MOSFET gate driver (IC) losses;
= total lower MOSFET gate charge at V
R2 +
%master
R +
R1(1 * Ratio)
C6 · RL
, input power ratio
Ratio
L
http://onsemi.com
CC
L
time
;
NCP5424
14
Current Sharing Errors
layout imbalances, inductor mismatch, and input offsets in
the error amplifiers. The first two sources of error can be
controlled through careful component selection and good
layout practice. With a 4.0 mW inductor, for example, one
mV of input offset error will represent .25 A of error. One
way to diminish this effect is to use higher resistance
inductors but the penalty is higher power losses in the
inductors. Fortunately, the input offset of the NCP5424 is
low so that this error term is reduced.
Current Sharing Compensation Capacitor Selection
applications. Therefore the IC needs two separate
compensation capacitors for the dual output designs, which
is not desirable for a single output design. With two
compensation capacitors, a race condition between the
master and slave controllers is created. During start−up or
upon leaving Hiccup mode, the Master’s Error Amplifier
starts charging Comp1. When Comp1 reaches 0.40 V, both
controllers begin to regulate the output. The Slave
Controller voltage reference is generated externally by the
Master’s output, while the Master has an internal 1.0 V
reference. Since Comp2 does not start charging until Comp1
reaches 0.40 V, the Slave’s PWM inverting input is lower
than its Vfb−2 input causing a reset of the Slave Controller
output driver. Gate(L)2 turns on, sinking current from the
output, while the Master’s output driver is set turning
Gate(H)1 on and sourcing current to the output (since its
PWM inverting input is higher than its Vfb1 input). This
condition will continue until Comp2’s amplitude is equal to
Comp1’s. During this condition, the output voltage is being
shorted to ground through the bottom FET, on the slave side.
In hiccup mode, if this shoot−through current is large
enough to develop 70 mV across L1, the Controllers will
remain in hiccup mode even after the external load or short
is removed. To avoid this condition, the Comp2 ramp’s rise
time is increased to minimize the shoot−through current.
The value of the Comp2 capacitor is calculated by the
following equations.
where:
Comp2. If Soft−Start rise time is not an issue, a 0.22 mF
R17 = The inverting signal filter resistance.
The three main errors in current sharing arise from board
The NCP5424 is designed for single and dual output
C8 = Comp1 capacitor value, 0.22 mF is suggested.
R
R
A good rule of thumb is a 20 to 1 ratio between Comp1 and
L2
fet
= R
=Inductor parasitic resistance (LSR), see inductor’s
data sheet.
DS(on)
C13 +
of the Slave’s lower FET, see data sheet.
R X + R L2 ) R fet
R17 v R1 · R2
(0.07 · 25%) · R X
0.45 · R L2
R1 ) R2
C8
) 1