adp3811 Analog Devices, Inc., adp3811 Datasheet - Page 15

• Manufacturer Part Number: adp3811
• Description: Secondary Side, Off-line Battery Charger Controllers
• Manufacturer: Analog Devices, Inc.

Step 9. Iterate C
Because f
fier gain in a nonnegligible amount at the 0 dB point. The in-
crease in gain is calculated as:
Now, the total error amplifier gain loss required is:
With this, the new f
Step 5.
Finally, C
Following these steps gives a cookbook method for calculating
the compensation components for the voltage loop. As men-
tioned above, these components can be optimized in the actual
circuit. The results of a PSpice
Figure 32. The open loop gain of the loop is 108 dB as calcu-
lated. The crossover frequency is 100 Hz with a phase margin
of 52 . The graph shows the phase leveling off at 90 . In reality
the phase will continue to fall as higher frequency parasitic poles
take effect.
1
Voltage Loop Compensation, Battery Present
When the battery has finished charging and is still connected to
the charging circuitry, the system is said to be “floating” the bat-
tery. The loop is maintaining a constant output voltage equal to
the battery voltage, and the output current has dropped to
nearly zero. This case is actually the easiest to compensate be-
cause the battery’s capacitance creates a very low frequency
dominant pole, giving a single pole response. For example, if the
battery is modeled as a 10 Farad capacitor, the dominant pole
will be 1/(2
quency pole causes the system to cross over 0 dB at less than
10 Hz, giving a stable single pole system. The compensation
components have little effect on this response, so no further
calculations are needed for this case.
REV. 0
PSpice is a trademark of MicroSim Corporation.
–100
180
200
100
Figure 32. Voltage Loop Gain/Phase Plots
Z1
C1
90
0
0
0.01
is very close to f
is recalculated using the equation in Step 6.
G
C
LOSS
1.2 k
C1
C1
0.1
20 log 1
:
= 37.6 dB + 7.1 dB = 44.7 dB
P1
2
can be calculated from the equation in
400 k
10 F) = 0.013 MHz. This very low fre-
f
P1
1
CV
FREQUENCY – Hz
= 0.58 Hz
1
, it will increase the error ampli-
1
PHASE MARGIN = 52
f
f
analysis of the loop is shown in
CV
10
Z1
0.58 Hz
2
7.1dB
100
0dB CROSSOVER
0.7 F
1k
100k
–15–
Current Loop Compensation
Now that the voltage loop compensation is complete, it is time
to add the compensation for the current loop. The definitions
for modulator gain and error amplifier gain are the same as be-
fore; but now, the controlling error amplifier is GM1 in Figure
31, as opposed to GM2, for the voltage loop. Otherwise, the
calculations are very similar.
Step 10. Calculate the dc loop gain (G
Step 11. Pick the current loop crossover frequency, f
From Step 2 in the voltage loop calculations, f
Step 12. Calculate G
The modulator gain of –4.5 dB is the dc gain. The modulator
pole reduces this gain above f
If the 1 mF capacitor has a much higher ESR, e.g., 1 , the
modulator zero, f
lator pole, f
crease and could cause instability. One possible solution to this
scenario is to use a much higher value (47 nF) for the C
capacitor. The pole of this capacitor would then be in the 1 kHz
range and would reduce the loop gain. If the ESR is much less
than 0.1 , the bandwidth of the loop will decrease slightly.
Step 13. Calculate gain loss of G
The gain loss of G
loss due to C
calculate the contribution of gain roll-off needed from C
the effective gain of G
is calculated at 1.9 kHz, the impedance of C
the gain becomes:
G
MOD
G
G
f
G
EA
G
PM
MOD
G
= 38.9 dB – 13.4 dB = 25.5 dB
MOD
G
MOD
LOSS
1.9 kHz
1.9 kHz
f
EA
ZM
2
PM
20 log GM 3 ITX
1.9 kHz
G
C1
= G
. This causes the loop gain and bandwidth to in-
20 log
1.9 kHz
LOOP
, R
2
G
R
8.3 mA /V 400 k
ZM
EA
EA
CS
G
C1
EA
MOD
R
, will be lower in frequency than the modu-
20 log 8.3 mA /V
(1.9 kHz) – G
= –6.1 dB + 70.4 dB = 64.3 dB
1
and the additional loss from C
MOD
in the current loop is a combination of the
1
F1
R
20 log GM1 R5
EA
6 mA /V 0.36 3.3 k
0.333 1.0 A /V 0.25
F1
20 log GM1
dc
must first be calculated. Since the gain
C
at f
4.5 dB 12.7 dB 3.8 dB –13.4 dB
F1
C
20 log 1
CI
F1
PM
ADP3810/ADP3811
2
:
.
OC
2
MOD
EA
0.1
at f
R
0.35
1
70.4 dB
(1.9 kHz)
F
f
R6 R
LOOP
f
PM
CI
CI
10320
1
1mF
:
A
20 log
V 2
2
C1
), f
1mF
C1
CI
20 log 1
is 120 . Thus,
PM
GM 4 R
1.6 kHz
~ 1.9 kHz.
120
, and f
C2
4.5 dB
450 Hz
, R
38.9 dB
CI
F
C2
C2
ZM
CS
:
= 1 nF
f
. To
f
, R
ZM
:
CI
C2
2
,