adp3811 Analog Devices, Inc., adp3811 Datasheet - Page 14

• Manufacturer Part Number: adp3811
• Description: Secondary Side, Off-line Battery Charger Controllers
• Manufacturer: Analog Devices, Inc.

ADP3810/ADP3811
either present or absent. If the battery is present, its large ca-
pacitance creates a very low frequency dominant pole, giving a
single pole system. The more demanding case is when the bat-
tery is removed. Now the output pole is dependent upon the
filter capacitors, C
and more care must be taken to stabilize the loop response. All
three cases are described in detail below.
The following calculations for compensation components help
to realize stable voltage and current loops. In practical designs,
checking the stability using a network analyzer or a Feedback
Loop Analyzer is always recommended. The calculated compo-
nent values serve as good starting values for a measurement-
based optimization. The component values shown in Figure 23
are slightly different from the calculated values based on this
optimization procedure.
To simplify the analysis further, the loop gain is split into two
components: the gain from the battery to the ADP3810/
ADP3811’s COMP pin and the gain from the COMP pin back
to the battery. Because the compensation of each loop depends
upon the RC network on the COMP pin, it is a convenient
choice for dividing the loop calculations.
Definitions:
Modulator Gain: G
Error Amplifier: G
Loop Gain:
Modulator Pole: f
Modulator Zero: f
Voltage Loop Compensation, No Battery
Step 1. Calculate the dc loop gain (G
In reality, the interaction of C
an additional pole/zero pair, but because the value of R
of C
each other out. Furthermore, the loop crossover is an order of
magnitude lower in frequency, so the additional pole and zero
have little effect on the loop response.
G
f
PM
G
EA
F1
G
MOD
) and R
MOD
f
2
20 log
ZM
20 log
R4
20 log GM 3 ITX
G
2
F2
G
LOOP
EA
(ESR of C
80 k
V
G
modulator.
filter cap, C
1
R
F1
PM
ZM
C
BAT
1
F1
MOD
EA
LOOP
= 44.5 dB + 48.3 dB = 96.8 dB
F1
20 log
and C
, The pole present at the output of the
, The zero due to the ESR, R
20 k
6 mA / V
0.333 0.091 A / V 1.2 k
= gain in dB from V
.
C
C
= gain in dB from the COMP pin to
= G
20 k
F1
F2
F2
F2
MOD
) are similar, they tend to cancel
. This pole is higher in frequency,
2
F1
R1 R2
F1
2
.
R2
0.36 3.3 k
and C
OC
2.1mA /V 400 k
+ G
0.1
1.2 k
EA
R
1
F2
GM 2 R5
LOOP
.
F
1.0 mF
and their ESRs create
1
BAT
A
), f
V 2
1.22 mF
to the COMP pin.
PM
GM 4 R4
, and f
F1
1.6 kHz
, of the
48.3 dB
48.5 dB
0.11 Hz
F1
ZM
(ESR
:
–14–
Step 2. Pick the voltage and current loop crossover frequen-
cies, f
To avoid interference between the voltage loop and the current
loop, use f
rent loop crossover f
fast current limiting response time, so pick f
Step 3. Calculate G
The modulator gain of 46.7 dB is the dc gain. The modulator
pole reduces this gain above f
Step 4. Calculate gain loss of G
To have the feedback loop gain cross over 0 dB at f
G
G
Step 5. Determine f
To achieve this G
the COMP pin. GM2 has practically no parasitic loss in
gain at 100 Hz. Its first parasitic pole occurs at approximately
500 kHz as shown in Figure 11. Thus, the entire gain loss must
be realized with an external compensation capacitor, C
sets the pole, f
Step 6. Calculate C
Step 7. Calculate the loop phase margin,
The loop phase margin is a combination of the phase of the
modulator pole and zero and the error amplifier pole.
Step 8. Calculate R
The sum of phase losses of the modulator and error amplifier re-
sults in a loop phase of 0 , which is unacceptable for loop stabil-
ity. To stabilize the feedback loop, we have to add a phase
boosting zero to the error amplifier by inserting a resistor (R
in series with the capacitor C
From this, the R
G
M
EA
EA
LOSS
G
= 60 degrees, the frequency of the zero can be calculated:
(100 Hz) should be +10.9 dB. Thus, the total gain loss of
needed at crossover is:
M
MOD
CV
= G
G
180 arc tan
and f
MOD
(100 Hz) 48.3 dB 20 log 1
CV
EA
< 1/10 of f
(dc) – G
CI
(100 Hz ) G
P1
:
.
C1
LOSS
C
f
R
resistor is calculated:
P1
C1
CI
f
MOD
C1
C1
P
C1
Z1
EA
needed to achieve G
we need to add a pole, which is located at
f
is chosen to be ~ 1.9 kHz to provide a
based upon f
f
to stabilize the loop:
= f
CV
P1
CI
(100 Hz) = 48.5 dB – 10.9 dB = 37.6 dB
2
at f
2
10
, the current loop crossover. The cur-
CV
MOD
/tan
CV
G
R5 f
C1
f
arc tan
PM
f
LOSS
CV
10
1
:
Z1
1
. If the desired phase margin is
(dc) 20 log 1
.
EA
M
C
P1
at f
C1
= 57 Hz
1
P
:
f
f
PM
CV
CV
1.3 Hz
0.3 F
10 k
:
LOSS
CV
100
0.11
arc tan
M
:
~ 100 Hz.
:
2
f
f
CV
CV
PM
f
f
CV
ZM
10.9 dB
= 100 Hz,
C1
2
, that
REV. 0
0
C1
)