ncp1927 ON Semiconductor, ncp1927 Datasheet - Page 22

• Manufacturer Part Number: ncp1927
• Description: Combination Power Factor Correction Controller And Flyback Controller For Flat Panel Tvs
• Manufacturer: ON Semiconductor

Go To Standby Pin
stage during system standby based on the flyback stage load
condition. This can be done by connecting it to the flyback
stage feedback pin (FFB) through a resistor divider or by
directly driving the pin with an optocoupler. These
implementations are shown in Figures 29 and 30.
(typically 200 kW), for use with an optocoupler and to assure
the PFC is disabled if the pin is floating.
GTS power level threshold. When V
the GTS threshold, V
switching and enter standby mode. It remains in standby
until V
(V
transients on the flyback converter do not trigger GTS.
However, the PFC must come out of standby as soon as
possible if there is a request to turn on the TV. Therefore, the
timer is bypassed when coming out of standby. The FFB
voltage at which the PFC enters GTS is expressed using
Equation 21.
where R
R
GTS pin can instead be driven with an optocoupler from the
secondary side to force the PFC stage in and out of standby
mode. A resistor (R
optocoupler to limit the current into the GTS pin.
GTS2
The Go To Standby (GTS) pin is used to disable the PFC
The GTS pin contains an internal pull down resistor, R
The resistor divider from the FFB pin is used to setup the
If direct control of the PFC standby mode is desired, the
Figure 29. GTS Implementation with Feedback Pin
standby(HYS)
and is calculated using Equation 22.
GTS
equiv
GTS
V
is brought above the hysteresis of V
FFB(GTS)
is the parallel resistor combination of R
). A timer is included on the GTS pin to ensure
R
equiv
+ V
limit
+
standby
GTS
) is placed in series with the
R
R
GTS
GTS
, the PFC controller stops
@
FFB
R
) R
@ R
C
GTS1
GTS
GTS2
R
GTS2
GTS
equiv
) R
is brought below
R
R
equiv
GTS1
GTS2
(eq. 21)
(eq. 22)
GTS
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standby
GTS
and
22
IENABLE Pin
that enables the Flat Panel TV backlight inverter once the
PFC stage reaches regulation. The NCP1927 achieves this
by monitoring the current sourced by the EA. Once this
current drops to 0 mA, the IENABLE pin voltage switches
to V
in Figure 31.
the inverter from undervoltage conditions by detecting
when the PFB voltage falls below V
the IENABLE pin voltage switches to V
the result from Equation 7, the output threshold that sets the
IENABLE pin low can be calculated with Equation 23.
where V
To filter noise, a decoupling capacitor (C
connected to the pin.
The IENABLE pin is designed to drive an optocoupler
A separate comparator on the PFB pin is used to protect
The IENABLE pin can also be used as a voltage reference.
Figure 30. GTS Implementation with Optocoupler
V
V
V
V
VCC_AUX
IENABLE(high)
−20 μA
out(MAX)
out(NOM)
I
out(MIN)
EA(out)
IENABLE
0 μA
V
0 V
5 V
out
disable
from secondary side
Figure 31. IENABLE Pin Timing
Inverter
Starts
is the disable threshold (1.865 V typical).
V
out(disable)
(typically 5.0 V). This operation is shown
Undershoot from Inverter
+
R
V
limit
out
Load
V
@ V
disable
REF
disable
C
GTS
IENABLE(low)
GTS
. When this occurs,
REF
) may be
(eq. 23)
time
time
. Using
time