ncp1927 ON Semiconductor, ncp1927 Datasheet - Page 21

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ncp1927

Manufacturer Part Number
ncp1927
Description
Combination Power Factor Correction Controller And Flyback Controller For Flat Panel Tvs
Manufacturer
ON Semiconductor
Datasheet

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Skip Mode Operation
the power demand drops below a given level. This is
accomplished by monitoring the internal offset PControl
voltage. This voltage is compared to the PCT ramp to control
the power level in a particular design. During normal
operation, the circuit generates the input line current
necessary for matching the load power demand. If the need
for power decreases, the regulation loop lowers the
regulation voltage to reduce the power delivery accordingly.
When the regulation voltage goes below a programmable
pre−set level, the PFC stage stops switching. This causes the
output voltage to decrease, and the regulation voltage to
increase. When the regulation voltage exceeds the skip
threshold, switching resumes.
for 10% of the time, as opposed to 1% power for 100% of the
time. This skip cycle mode, also called controlled burst
operation, is much more efficient than a continuous power
flow since it drastically reduces the number of switching
pulses and their associated switching losses. To ensure
stability, hysteresis is added.
levels by connecting it through a single resistor to ground.
Since the skip threshold power levels can vary with line
voltage, they are calculated using Equations 18 and 19.
The NCP1927 automatically skips switching cycles when
This operation allows the PFC stage to deliver 10% power
The PSKIP pin provides the possibility to adjust these
PControl
PFAULT
SKIP
OTA Output
Figure 28. Schematic for PSKIP Pin
http://onsemi.com
PFC_OK
21
9*R
R
where V
is the minimum ac line voltage, Vac is the operating line
voltage, and P
ground using Equation 20.
where I
(30 mA typical) and R
to ground.
the PSKIP pin directly to ground. If the PSKIP pin is left
floating, V
and disable the drive. Since the PControl Pin is low during
startup, the PFC skip mode is disabled until the PFC output
reaches regulation and the IENABLE Pin is high. A
simplified schematic of the PSKIP pin is shown in
Figure 28.
The skip pin voltage is adjusted through a resistor to
If desired, skip mode can be easily disabled by connecting
To PWM Comparator
PSKIP
PSKIP
P
P
skip(upper)
PSKIP
skip(lower)
out(MAX)
is the voltage applied to the PSKIP pin, Vac
is the value of the internal current source
V
will rise towards the internal voltage rail
PSKIP
V DD
+
+
PSKIP
4.5 V @
5 V @
is the maximum output power.
+ I
PSKIP
V
V
is the external resistor connected
PSKIP
PSKIP
PSKIP
Vac
Vac
Vac
Vac
LL
@ R
LL
2
PSKIP
2
@ P
R PSKIP
@ P
out(MAX)
out(MAX)
(eq. 18)
(eq. 19)
(eq. 20)
LL

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