lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 6

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F008SC
Data Protection
may choose to make the V
(available only when memory block erases, byte writes,
or lock-bit configurations are required) or hardwired to
V
tice and encourages optimization of the processor-
memory interface.
altered. The CUI, with two-step block erase, byte write,
or lock-bit configuration command sequences, provides
protection from unwanted operations even when high
voltage is applied to V
when V
when RP
provides additional protection from inadvertent code or
data alteration by gating erase and byte write
operations.
BUS OPERATION
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Read
codes, or status register independent of the V
age. RP
command (Read, Array, Read Identifier Codes, or Read
Status Register) to the CUI. Upon initial device power-
up or after exit from deep power-down mode, the de-
vice automatically resets to read array mode. Four
control pins dictate the data flow in and out of the com-
ponent: CE
driven active to obtain data at the outputs. CE
device selection control, and when active enables the
selected memory device. OE
(DQ
memory data onto the I/O bus. WE
RP
cycle.
Output Disable
are disabled. Output pins DQ
high-impedance state.
6
PPH1/2/3
Depending on the application, the system designer
When V
The local CPU reads and writes flash memory
Information can be read from any block, identifier
The first task is to write the appropriate read mode
With OE
»
must be at V
0
- DQ
CC
»
can be at either V
. The device accommodates either design prac-
»
is at V
7
»
is below the write lockout voltage V
) control and when active drives the selected
PP
»
, OE
at a logic-high level (V
IL
»
V
, WE
IH
. The device’s block locking capability
PPLK
or V
PP
»
, and RP
, memory contents cannot be
HH
. All write functions are disabled
. Figure 15 illustrates a read
IH
PP
or V
power supply switchable
0
»
. CE
- DQ
»
HH
IH
is the data output
»
), the device otuputs
.
must be at V
»
7
and OE
are placed in a
»
must be
PP
»
LKO
IH
is the
volt-
and
or
Standby
standby mode which substantially reduces device power
consumption. DQ
impedance state independent of OE
ing block erase, byte write, or lock-bit configuration, the
device continues functioning, and consuming
active power until the operation completes.
Deep Power-Down
output drivers in a high-impedance state and turns off
all internal circuits. RP
of 100 ns. Time t
down until initial memory access outputs are valid. Af-
ter this wake-up interval, normal operation is restored.
The CUI is reset to read array mode and status register
is set to 80H.
tion modes, RP
remains low until the reset operation is complete.
Memory contents being altered are no longer valid; the
data may be partially erased or written. Time t
required after RP
other command can be written.
assert RP
out of reset, it expects to read from the flash memory.
Automated flash memories provide status information
when accessed during block erase, byte write, or lock-
bit configuration modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may not
occur because the flash memory may be providing sta-
tus information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP
application, RP
nal that resets the system CPU.
Read Identifier Codes Operation
facturer code, device code, block lock configuration
codes for each block, and the master lock configuration
code (see Figure 5). Using the manufacturer and de-
vice codes, the system CPU can automatically match
the device with its proper algorithms. The block lock and
master lock configuration codes identify locked and
unlocked blocks and master lock-bit setting.
CE
RP
In read modes, RP
During block erase, byte write, or lock-bit configura-
As with any automated device, it is important to
The read identifier codes operation outputs the manu-
»
»
at V
at a logic-high level (V
»
during system reset. When the system comes
IL
initiates the deep power-down mode.
PHQV
»
»
is controlled by the same RESET sig-
- low will abort the operation. RY
0
»
goes to logic-high (V
- DQ
»
- low deselects the memory, places
is required after return from power-
»
must be held low for a minimum
7
outputs are placed in a high-
8M (1M × 8) Flash Memory
IH
) places the device in
»
. If deselected dur-
IH
»
input. In this
) before an-
PHWL
»
/ BY
is
»