lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 13

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

8M (1M × 8) Flash Memory
Write Protection Alternatives
Status Register Definition
Block Erase or
Byte Write
Set Block
Lock Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
OPERATION
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
WSMS
7
= WRITE STATE MACHINE STATUS
= ERASE SUSPEND STATUS
= ERASE AND CLEAR LOCK-BIT STATUS
= BYTE WRITE AND SET LOCK-BIT STATUS
= V
= BYTE WRITE SUSPEND STATUS
= DEVICE PROTECT STATUS
= RESERVED FOR FUTURE ENHANCEMENTS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
1 = Error in Byte Write or Set Master/Block Lock Bit
0 = Successful Byte Write or Set Master/Block
0 =
1 = V
0 = V
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
1 = Master Lock-Bit, Block Lock-Bit and/or
1 =
0 = Unlock
PP
RP
Lock-Bit
STATUS (VPPS)
PP
PP
LOCK-BIT
»
MASTER
Lock Detected, Operation Abort
Low Detect, Operation Abort
OK
ESS
6
X
X
0
1
0
1
LOCK-BIT
BLOCK
ECLBS
0
1
X
X
X
X
X
5
V
V
V
IH
IH
IH
RP#
V
V
V
V
V
V
V
V
or V
or V
or V
BWSLBS
HH
HH
HH
HH
IH
IH
IH
IH
4
HH
HH
HH
Block Erase and Byte Write Enabled.
Block is locked. Block Erase and Byte Write Disabled.
Block Lock-Bit Override. Block Erase and Byte Write Enabled.
Set Block Lock-Bit Enabled.
Master Lock-Bit is Set. Set Block Lock-Bit Disabled.
Master Lock-Bit Override. Set Block Lock-Bit Enabled.
Set Master Lock-Bit Disabled.
Set Master Lock-Bit Enabled.
Clear Block Lock-Bits Enable.
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled.
Master Lock-Bit Override. Clear Block Lock-Bits Enabled.
NOTES:
1. Check RY
2. If both SR.5 and SR.4 are '1's after a block erase or lock-
3. SR.3 does not provide a continuous indication of V
4. SR.1 does not provide a continuous indication of master
5. SR.0 is reserved for future use and should be masked out
VPPS
write, or lock-bit configuration completion. SR.6 - SR.0 are
invalid while SR.7 = '0'.
bit configuration attempt, an improper command sequence
was entered.
The WSM interrogates and indicates the V
after Block Erase, Byte Write, Set Block/Master Lock-Bit,
or Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to report accurate feedback only when
V
and block lock-bit values. The WSM interrogates the master
lock-bit, block lock-bit, and RP
Write, or Lock-Bit configuration command sequences. It
informs the system, depending on the attempted operation,
if the block lock-bit is set, master lock-bit is set, and/or RP
is not V
ration codes after writing the Read identifier Codes com-
mand indicates master and block lock-bit status.
when polling the status register.
3
PP
= V
HH
PPH1/2/3
»
. Reading the block lock and master lock configu-
/ BY
»
or SR.7 to determine block erase, byte
.
BWSS
2
EFFECT
»
only after Block Erase, Byte
DPS
1
PP
level only
LH28F008SC
PP
R
0
level.
»
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