w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 63

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

IR FIFO Control Register (UFR):
Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
Bit 2:
Bit 1:
Bit 0:
Legacy IR RXFTL1
Advanced
Reset Value
MODE
IR
the interrupt active level is set as 4 bytes and there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
Advanced SIR/ASK-IR modes:
MIR, FIR modes:
Remote Controller Mode: Not used.
USR_I - IR Status Interrupt.
Set to 1 when overrun error, parity error, stop bit error, or silent byte error is detected and
registered in the IR Status Register (USR). Cleared to 0 when USR is read.
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is
defined in the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been
detected during receiving valid data. Cleared to 0 when this register is read.
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this
register is read.
RXTH_I - Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the
threshold level; or (2) RBR time-out occurs if the receiver buffer register has valid data
and is below the threshold level. Cleared to 0 when RBR is less than threshold level
after reading RBR.
RXFTL1
(MSB)
(MSB)
BIT 7
0
RXFTL0
RXFTL0
(LSB)
(LSB)
BIT 6
0
TXFTL1
(MSB)
BIT 5
0
0
TXFTL0
(LSB)
BIT 4
- 55 -
0
0
W83977ATF/W83977ATG
BIT 3
0
0
0
Publication Release Date: May 2006
TXF_RST RXF_RST EN_FIFO
TXF_RST RXF_RST EN_FIFO
BIT 2
0
BIT 1
0
Revision 0.6
BIT 0
0