w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 123

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

12.3 ACPI Registers (ACPIRs)
The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A
register block may be an event register block which deals with ACPI events or a control register block
which deals with control features. The order in the event register block is a status register followed by
an enable register.
Each event register, if implemented, contains two registers: a status register and an enable register, of
16 bits wide each. The status register indicates which event triggers the ACPI System Control
Interrupt ( SCI ). When the hardware event occurs, the corresponding status bit will be set. However,
the corresponding enable bit is also required to be set before an SCI interrupt can be raised. If the
enable bit is not set, the software can examine the state of the hardware event by reading the status
bit without generating an SCI interrupt.
Any status bit, unless otherwise noted, can only be set by specific hardware events. It is cleared by
writing a 1 to its bit position, and writing a 0 has no effect. Except for some special status bits, every
status bit has a corresponding enable bit on the same bit position in the enable register. Those status
bits which have no corresponding enable bit are read for special purpose. Reversed or
unimplemented enable bits always return zero, and writing to these bits should have no effect.
The control bit in the control register provides some special control functions over hardware events, or
some special control over SCI event. Reserved or unimplemented control bits always return zero,
and writing to those bits should have no effect.
Table 12-1 lists the PM1 register block and the registers within it. The base address of PM1 register
block is named as PM1a_EVT_BLK in the ACPI specification and is specified in CR60, CR61 of
logical device A.
Table 12-2 lists the GPE register block and the register within it. The base address of general-purpose
event block GPE0 is named as GPE0_BLK in the ACPI specification and is specified in CR62, CR63
of logical device A. The base address of general-purpose event block GPE1 is named as GPE1_BLK
in the ACPI specification and is specified in CR64, CR65 of logical device A.
12.3.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
Default Value:
Attribute:
Size:
<CR60, 61> System I/O Space
00h
Read/write
8 bits
7
6
5
4
3
- 115 -
2
W83977ATF/W83977ATG
1
0
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
Publication Release Date: May 2006
Revision 0.6