w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 96

• Manufacturer Part Number: w83637hg
• Description: Winbond Lpc I/o Lpc I/o
• Manufacturer: Winbond Electronics Corp America

Bit 4: SBD means silent byte detected. This bit is set to "1" to indicate that received data byte are
Bit 3: NSER means no stop bit error. This bit is set to "1" to indicate that received data has no stop
Bit 2: PBER means parity bit error. This bit is set to "1" to indicate that parity bit of received data is
Bit 1: OER means overrun error.
Bit 0: RDR means receiver data ready. This bit is set to "1" to indicate received data is ready to be
Guard Time Register (GTR at base address + 6, default 01h)
This register specifies number of stop bits appended in the end of data byte.
Bit 7 ~ 0: Guard time values. Default to be 01h.
kept in silent state for a full byte time, including start bit, data bits, parity bit, and stop bits. In
FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads
SCSR, it clears this bit to "0".
bit. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host
reads SCSR, it clears this bit to "0".
wrong. In FIFO mode, it indicates the same condition for the data on top of the FIFO. When
host reads SCSR, it clears this bit to "0".
overwritten by the next received data before it is read by host. In FIFO mode, it indicates the
same condition instead of FIFO full. When host reads SCSR, it clears this bit to "0".
read by host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is cleared to "0".
7
6
5
This bit is set to "1" to indicate previously received data is
4
3 2
1
- 91 -
0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Publication Release Date: March, 2006
W83637HF/HG
Revision 1.6