w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 89

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w83637hg

Manufacturer Part Number
w83637hg
Description
Winbond Lpc I/o Lpc I/o
Manufacturer
Winbond Electronics Corp America
Datasheet

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Receiver Buffer Register (RBR at base address + 0 when BDLAB = 0, read only)
This register is the access port for receiver FIFO. It is active when Smart Card interface is in input
mode with SCIODIR (bit 1 of ECR at base address + 7) set to "1". The depth of receiver FIFO is 16
bytes.
Bit 7 ~ bit 0: Access port for receiver FIFO.
Receiver Buffer Register (RBR at base address + 0 when BDLAB = 0, read only)
This register is the access port for transmitter FIFO. It is active when Smart Card interface is in output
mode with SCIODIR (bit 1 of ECR at base address + 7) set to "0". The depth of transmitter FIFO is 16
bytes.
Bit 7 ~ bit 0: Access port for receiver FIFO.
7
7
6
6
5
5
4
4
3 2
3 2
1
1
- 84 -
0
0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Publication Release Date: March, 2006
W83637HF/HG
Revision 1.6

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