sta002 STMicroelectronics, sta002 Datasheet - Page 25

• Manufacturer Part Number: sta002
• Description: Starmano Channel Decoder
• Manufacturer: STMicroelectronics

b2 : Illegal Address on
b3 : TDM out of frame on
b4 : RS block error on
b5 : SCH interrupt on
b6 : Test purpose
Reg name: STATUS REG
Internal address: 20EH
Type: R
Reset Value: 00H
Description: Status register:
b0 : TSCC available
b1 : BC lock
b2 : SCH available
b3 : PRC lock
b4 : MFP lock
b5 : SCCF available
5. VITERBI DECODER AND SYNCHRONIZATION
A Viterbi decoder has been implemented in the
STA002 in order to extract the most probable
transmitted sequence using a trace back proce-
dure.
This Viterbi decoder has been realized using 64-
bit trace back depth and the soft decision ap-
proach on the six-bit I and Q components coming
from the QPSK demodulator.
The convolutive codes are generated by the poly-
nomials Gx = 171
The Viterbi decoder computes for each symbol
the metrics of the four possible paths, propor-
tional to the square of the Euclidian distance be-
tween the recived I and Q and the theoretical
symbol value.
Four logical RAM banks (implemented with eight
RAM blocks of 32x64 bits) have been used for
the path memory.
The decoding latency is 256 bits.
A bit error (BER) estimator has been integrated in
the Viterbi block.
Corrected data bits at Viterbi output are encoded
according to the transmission convolutional code
so that a "good" stream is obtained. These data
are compared with the data stream coming from
the QPSK demodulator after having stored it into
a memory buffer to compensate the Viterbi la-
MSB
X
X
b5
oct
and Gy = 133
b4
b3
b2
oct
.
b1
LSB
b0
tency.
The number of wrong bits is accumulated into a
register according to a given time base ex-
pressed in number of bits and, assuming that the
BER at the output of the Viterbi decoder is negli-
gible with respect to the input BER, this count can
be read by the system micro controller to evalu-
ate the signal quality after QPSK demodulation.
The error rate measurement is programmable
throught the VITERBI_ERROR_CONTROL regis-
ter and the error rate is available in the registers:
- VIT_
- VIT_
Reg name: VITERBI_ERROR_CONTROL
Internal address: 204 H
Type: R/W
Reset Value: 00H
Description: Viterbi input errors measurement
windows length and error mode presetting.
Reg name: VIT_ERR0R1, VIT_ERROR2
Internal address: 213 H , 214H
Type: R/W
VIT_ERROR 1 (ERROR COUNTER LOW)
VIT_ERROR 2 (ERROR COUNTER HIGH)
Description: Viterbi error counter register
MSB
MSB
MSB
b1b0 =
b2
b2
b3
b3
A15
A7
X
ERROR
ERROR 2
=
=
=
=
A14
A6
X
00
01
10
11
0
1
0
1
1
A13
A5
X
Monitor windows length (bits)
1024
4096
16384
65536
Error Measurement Mode
Single acquisition mode
Continuous acquisition mode
End measurement (single /continuous
acquisition )
Single acquisition start
A12
A4
X
A11
A3
b3
A10
A2
b2
A1
A9
b1
STA002
LSB
LSB
LSB
25/43
A0
A8
b0