sta002 STMicroelectronics, sta002 Datasheet - Page 15

• Manufacturer Part Number: sta002
• Description: Starmano Channel Decoder
• Manufacturer: STMicroelectronics

b3, b2: Test purpose
2.2 A/D CONVERTER
This block performs the analog to digital conver-
sion of the incoming IF input signal.
The ADC has a resolution of 6 bit and is based
on the so called Half Flash architecture to reduce
both area and power consumption.
The sampling rate depends on the M_CLK (Mas-
ter Clock) frequency and on the PLL presetting.
3. QPSK DEMODULATOR
3.1 QUADRATURE DEMODULATOR
The final base-band demodulation is performed in
this block.
The samples of the IF input signal are multiplied
by the sine and cosine functions to get the two in-
phase (I) and quadrature (Q) components of the
QPSK signal. The phase ambiguity inherent in
QPSK is solved in the frame synchronisation part.
A programmable bit allows to multiply by -1 the
quadrature component in order to accomodate
QPSK modulation with another convention of ro-
tation sense (this is equivalent to a permutation of
I and Q components).
The sine and cosine functions are generated by
an NCO using a phase accumulator and a look-
up table.
3.2. INTERPOLATOR NYQUIST FILTER
The I and Q components are filtered by a digital
Nyquist root filter with the following features:
Separate I and Q stream, Fck/Fsym samples per
symbols;
Raised root cosine shape with roll-off factor of
40%;
Separate I and Q output stream, 1 sample per
symbol.
This filter performs both the Nyquist filter function
(matched with the one in the transmission side)
and the interpolation function to compute the opti-
mum output sample.
b1
b5
0
0
1
1
0
0
1
1
b0
b4
0
1
0
1
0
1
0
1
M_CLK (pin 9)
2XM_CLK (pin9)
Test purpose
Test purpose
Normal function (from ERROR_REG)
BC_LOCK signal on INTR pin
MFP_LOCK signal on INTR pin
PRCP_ALL_LOCK on INTR pin
PLL output clock (ADC input)
INTR pin control
3.3. TIMING RECOVERY
The timing loop is completely implemented digi-
tally and comprises the timing detector working at
symbol rate, a loop filter, the timing NCO and the
Nyquist/interpolator filters.
The loop is controlled by two parameters, al-
pha_tmg
TIMFLTPAR register.
3.3.1 Timing loop registers
Timing
(TIMFLTPAR)
Internal address: 8D H
Reset Value: 48H
Timing frequency registers (TIMINTG)
Internal address: 8E H
Reset Value: 0AH
The value of this register, when the system is
locked, is an image of the frequency offset.
Timing NCO frequency setting (SYMFREQ)
Internal address: 8C H 8B H 8A H
Reset Value
SYMFREQ3
SYMFREQ2
SYMFREQ1
This register is divided into three bytes. The LSB
byte is named SYMFREQ1, the MSB is named
SYMFREQ3.
MSB
MSB
MSB
MSB
MSB
b23
b15
b7
b7
b7
alpha_tmg
b22
b14
b6
b6
b6
loop
and
b21
b13
b5
b5
b5
: 0CH 11H D3H
beta_tmg
signed number
filter
b20
b12
b4
b4
b4
b19
b11
b3
b3
b3
parameter
contained
b18
b10
beta_tmg
b2
b2
b2
b17
b1
b1
b9
b1
STA002
register
in
LSB
LSB
LSB
LSB
LSB
b16
15/43
b0
b0
b8
b0
the