sta002 STMicroelectronics, sta002 Datasheet - Page 14

• Manufacturer Part Number: sta002
• Description: Starmano Channel Decoder
• Manufacturer: STMicroelectronics

STA002
1.5.5 TDM_MULTIPLEX Registers (continued)
1.5.6 TSCC_MEM Registers
2. IF INTERFACE
The Master Clock (M_CLK) is the source of all
the STA002 internal timings.
M_CLK is internally divided to drive the A/D con-
verter and to provide the clock signal for the
QPSK block.
The IF input signal, centered at 1.84MHz, is over-
sampled at a frequency F
M_CLK/2 according to STA002 presettings.
2.1 PLL
This fully integrated PLL includes the phase/fre-
quency detector, the charge pump, the filter and
14/43
HEX_COD
HEX_COD
237EH
3BCH
3BDH
3BEH
22EH
23CH
23DH
3BFH
3C0H
3C1H
22FH
230H
231H
232H
233H
234H
235H
236H
237H
300H
301H
302H
303H
304H
305H
306H
307H
DEC_COD
DEC_COD
558
559
560
561
562
563
564
565
566
567
568
569
570
768
769
770
771
772
773
774
775
956
957
958
959
960
961
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TEST_PURPOSE
TEST_PURPOSE
TEST_PURPOSE
TSCW 1 (7:0)
TSCW 1 (15:8)
TSCW 2 (7:0)
TSCW 2 (15:8)
TSCW 3 (7:0)
TSCW 3 (15:8)
TSCW 4 (7:0)
TSCW 4 (15:8)
TSCW 95 (7:0)
TSCW 95 (15:8)
TSCW 96 (7:0)
TSCW 96 (15:8)
TSCW ID (7:0)
TSCW ID (15:8)
ck
of M_CLK/4 or
REGISTER NAME
REGISTER NAME
the VCO.
The PLL output frequency F
I
Reg. name: PLL_INT_REG
Internal address: 21E H
Reset Value
Type: R/W
Description: PLL and INTR pin control register
2
MSB
C interface according to the PLL_INT_REG.
X
X
b5
: 00H
b4
b3
ck
TYPE
TYPE
can be selected via
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
b2
b1
VALUE
VALUE
RESET
RESET
0EH
0CH
1CH
0AH
0BH
2AH
12H
32H
2FH
09H
09H
09H
09H
LSB
b0