mpc755ed Freescale Semiconductor, Inc, mpc755ed Datasheet - Page 37

• Manufacturer Part Number: mpc755ed
• Description: Risc Microprocessor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

The MPC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the MPC755. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop
(DLL) circuit and should be routed from the MPC755 to the external RAMs. A separate clock output,
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin
L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the
clocking of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the
frequency of the MPC755 core, and the phase adjustment range that the L2 DLL supports.
various example L2 clock frequencies that can be obtained for a given set of core frequencies. The
minimum L2 frequency target is 80 MHz.
Freescale Semiconductor
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
4. In PLL off mode, no clocking occurs inside the MPC755 regardless of the SYSCLK input.
PLL_CFG
or VCO frequencies which are not useful, not supported, or not tested for by the MPC755; see
AC Specifications,”
bus mode is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
Table 16. MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts (continued)
0011
1111
[0:3]
Core Frequency (MHz)
Multiplier
Bus-to-
Core
PLL off/bypass
for valid SYSCLK, core, and VCO frequencies.
PLL off
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
250
266
275
300
325
333
350
366
Multiplier
Core-to-
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
VCO
Table 17. Sample Core-to-L2 Frequencies
33 MHz
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
Bus
250
266
275
300
325
333
350
366
÷1
50 MHz
÷1.5
166
177
183
200
217
222
233
244
Bus
PLL off, no core clocking occurs
66 MHz
125
133
138
150
163
167
175
183
÷2
Bus
÷2.5
75 MHz
100
106
110
120
130
133
140
146
Bus
100
108
111
117
122
80 MHz
÷3
83
89
92
Section 4.2.1, “Clock
System Design Information
Bus
Table 17
100 MHz
Bus
shows
37