at43usb320a ATMEL Corporation, at43usb320a Datasheet - Page 58

• Manufacturer Part Number: at43usb320a
• Description: Full-speed Usb Microcontroller With An Embedded Hub
• Manufacturer: ATMEL Corporation

Data
Transmission
58
AT43USB320A
A block schematic of the UART transmitter is shown in Figure 19.
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register, UDR. Data is transferred from UDR to the Transmit shift register when:
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If the 10-bit Transmitter shift register is empty, data is transferred from UDR to the shift regis-
ter. At this time the UDR E (UART Data Register Empty) bit in the UART Status Register,
USR, is set. When this bit is set (one), the UART is ready to receive the next character. At the
same time as the data is transferred from UDR to the 10-bit shift register, bit 0 of the shift reg-
ister is cleared (start bit) and bit 9 is set (stop bit).
On the baud rate clock following the transfer operation to the shift register, the start bit is
shifted out on the TXD pin. The n follows the data, LSB first. When the stop bit has been
shifted out, the shift register is loaded if any new data has been written to the UDR during the
transmission. During loading, UDRE is set. If there is no new data in the UDR register to send
when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When
no new data has been written and the stop bit has been present on TXD for one bit length, the
TX Complete flag (TXC) in USR is set.
The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is cleared
(zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will
be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1
bit in DDRD.
A new character has been written to UDR after the stop bit from the previous character
has been shifted out. The shift register is loaded immediately.
A new character has been written to UDR before the stop bit from the previous character
has been shifted out. The shift register is loaded when the stop bit of the character
currently being transmitted has been shifted out.
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