dsp56366 Freescale Semiconductor, Inc, dsp56366 Datasheet - Page 78

• Manufacturer Part Number: dsp56366
• Description: Dsp56366 24-bit Audio Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

3.13.1
The programmed serial clock cycle, T
HCKR (SHI clock control register).
The expression for T
where
In I
to
The programmed serial clock cycle (T
in order to achieve the desired SCL serial clock cycle (T
EXAMPLE:
For DSP clock frequency of 120 MHz (i.e. T
(F
Choosing HRS = 0 gives
Thus the HDM[7:0] value should be programmed to $41 (=65).
3-52
SCL
2
C mode, the user may select a value for the programmed serial clock cycle from
= 100 kHz (i.e. T
HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight
prescaler is operational. When HRS is set, the prescaler is bypassed.
HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256
(HDM[7:0] = $00 to $FF) may be selected.
Programming the Serial Clock
T
I
T
2
Table 3-21 SCL Serial Clock Cycle (T
I
CCP
2
I
Filters bypassed
Narrow filters enabled
Wide filters enabled
CCP
SCL
2
CCP
HDM 7:0
4096
is
= 10μs), T
6
=
=
×
T [
[
×
T
10μs 2.5 8.33ns
C
T
C
C
]
×
DSP56366 Technical Data, Rev. 3.1
I
I
=
2
2
2
if
R
–
CCP
CCP
×
if
= 1000ns), with wide filters enabled:
8756ns
HDM 7:0
(
, is specified by the value of the HDM[7:0] and HRS bits of the
HDM 7:0
), SCL rise time (T
HDM 7:0
×
C
= 8.33ns), operating in a standard mode I
[
⁄
[
[
2 (
]
T
T
T
×
]
–
]
=
I
I
I
2
2
2
8.33ns
CCP + 2.5
CCP + 2.5
CCP + 2.5
+
=
223ns 1000ns
SCL
$
1 )
02 and HRS
$
SCL
FF and HRS
), as shown in
×
R
) generated as Master
–
×
(
), and the filters selected should be chosen
7
8 ) 1
×
×
×
×
T
T
T
(
–
C
C
C
1 HRS
+ 45ns +
+ 135ns +
+ 223ns +
–
=
=
=
64.67
Table
=
1
8756ns
0
T
)
T
T
R
+
R
R
3-21.
1
)
]
Freescale Semiconductor
2
C environment