dsp56366 Freescale Semiconductor, Inc, dsp56366 Datasheet - Page 3

• Manufacturer Part Number: dsp56366
• Description: Dsp56366 24-bit Audio Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

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Freescale Semiconductor
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120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V.
Object Code Compatible with the 56K core.
Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic
support.
Program Control with position independent code support and instruction cache support.
Six-channel DMA controller.
PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors
(1 to 16) and power saving clock divider (2
Internal address tracing support and OnCE™ for Hardware/Software debugging.
JTAG port.
Very low-power CMOS design, fully static design with operating frequencies down to DC.
STOP and WAIT low-power standby modes.
7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.
13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.
40Kx24 Bit Program ROM.
3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as
Instruction Cache or for Program ROM patching.
2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM
resulting in up to 10Kx24 Bit of Program RAM.
External Memory Expansion Port.
Off-chip expansion up to two 16M x 24-bit word of Data memory.
Off-chip expansion up to 16M x 24-bit word of Program memory.
Simultaneous glueless interface to SRAM and DRAM.
Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I
AC97, network and other programmable protocols.
Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I
Sony, AC97, network and other programmable protocols
The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and
HCKT (high frequency clocks)
Features
DSP56300 Modular Chassis
On-chip Memory Configuration
Off-chip Memory Expansion
Peripheral Modules
DSP56366 Technical Data, Rev. 3.1
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: i=0 to 7). Reduces clock noise.
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S, Sony,
Overview
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S,